Electrostatic field limits and charge threshold for field-induced damage to voltage susceptible devices

We have studied electrostatic field and charge threshold limits for damage to MOSFET devices in order to understand the ESD damage risks during handling in electronics production and assembly processes. The study covers both field-induced charged device model (CDM) and charged board model (CBM) cases. The charging electrostatic field for failure can be even two orders of magnitude lower for a device on a board than at component level. The charge level for failure remains approximately constant. Our results show that charge threshold for failure would serve as a good guide for ESD risks of voltage susceptible MOSFETs as discrete components and when assembled to PWBs.     

An improvement to computational efficiency of the drain current model for double-gate MOSFET

As a connection between the process and the circuit design, the device model is greatly desired for emerging devices, such as the double-gate MOSFET. Time efficiency is one of the most important requirements for device modeling. In this paper, an improvement to the computational efficiency of the drain current model for double-gate MOSFETs is extended, and different calculation methods are compared and discussed. The results show that the calculation speed of the improved model is substantially enhanced. A two-dimensional device simulation is performed to verify the improved model. Furthermore, the model is implemented into the HSPICE circuit simulator in Verilog-A for practical application.     

第七讲微电子技术发展与物理学

微电子学的基础是近代固体物理．微电子技术的快速发展又推动了物理学许多分支的进展．今天，当微电子的基本器件MOSFET缩小接近其终极时，作为下一代的基础，一批基于新的物理效应的纳电子器件又被提了出来．为了突破传统的二值开关系统的共同极限，新的信息处理系统，如量子信息处理，正在大力研究之中．不久的将来，可望出现一次新的信息电子革命．这次革命又将建立在现代物理学及现代生物学的基础之上．     

Analytical modeling and simulation of subthreshold characteristics of back-gated SSGOI and SSOI MOSFETs: A comparative study

The Silicon–Germanium-on-Insulator (SGOI) and Silicon-on-Insulator (SOI) based MOS structures are spearheading the strained-Si technology. The present work compares the subthreshold characteristics of two short-channel back-gated (BG) strained-Si-on-SGOI (SSGOI) and BG strained-Si-on-Insulator (SSOI) MOSFETs, and provides some solutions to overcome the degradation in subthreshold characteristics with the unrelenting downscaling of the devices. Subthreshold behaviors of the MOS structures are based on surface potential model which is determined by solving the 2D Poisson's equation with suitable boundary conditions by evanescent mode analysis for both of the MOS structures. The closed form expressions for threshold voltage, subthreshold current and subthreshold swing have been derived for symmetrical as well as independent gate operation (IGO). In addition, the Electrostatic integrity (EI) factors for SSOI and SSGOI MOS structures have been estimated and compared with Double-Gate (DG) MOSFET. The numerical simulation results, obtained by ATLAS?, a 2D device simulator from Silvaco, have been used to assess the validity of the models.     

Effect of gate engineering in JLSRG MOSFET to suppress SCEs: An analytical study

In this work, an analytical model of gate-engineered junctionless surrounding gate MOSFET (JLSRG) has been proposed to uncover its potential benefit to suppress short-channel effects (SCEs). Analytical modelling of centre potential for gate-engineered JLSRG devices has been developed using parabolic approximation method. From the developed centre potential, the parameters like threshold voltage, surface potential, Electric Field, Drain-induced Barrier Lowering (DIBL) and subthershold swing are determined. A nice agreement between the results obtained from the model and TCAD simulation demonstrates the validity and correctness of the model. A comparative study of the efficacy to suppress SCEs for Dual-Material (DM) and Single-Material (SM) junctionless surrounding gate MOSFET of the same dimensions has also been carried out. Result indicates that TM-JLSRG devices offer a noticeable enhancement in the efficacy to suppress SCEs by as compared to SM-JLSRG and DM-JLSRG device structures. The effect of different length ratios of three channel regions related to three different gate materials of TM-JLSRG structure on the SCEs have also been discussed. As a result, we demonstrate that TM-JLSRG device can be considered as a competitive contender to the deep-submicron mainstream MOSFETs for low-power VLSI applications.     

A compact I－V model for lightly-doped-drain MOSFETs

A novel model for lightly-doped-drain (LDD) MOSFETs is proposed, which utilizes the empirical hyperbolic tangent function to describe the I－V characteristics. The model includes the strong inversion and subthreshold mechanism, and shows a good prediction for submicron LDD MOSFET. Moreover, the model requires low computation time consumption and is suitable for design of MOSFETs devices and circuits.     

Directed self-assembly process for nano-electronic devices and interconnect

Requirements for nano-electronic devices and interconnect in conventional logic circuit architecture are examined to reveal the possible device structure containing self-assembly (SA) features. For integration with lithography, we discuss the features of the SA process and then present a full process flow for a novel type of SA nano-crystal EEPROM cells. The logic functionality below the lithography limit derived from the SA dot arrays and the I–V characteristics including the Coulomb blockade effect are then presented.     

Turning the world vertical: MOSFETs with current flow perpendicular to the wafer surface

Tremendous progress in information technology has been made possible by the development and optimization of metal oxide semiconductor field effect transistor (MOSFET) devices. For the last three decades, the dimensions of the devices have been scaled down and the complexity of the integrated circuits increased according to Moore’s law. Further scaling of the devices has been predicted by the international technology roadmap for semiconductors (ITRS). To meet the future technological requirements, much effort has been expended on increasing the capabilities of MOSFETs. Both new materials and new designs have been introduced to maintain device scaling. Most new designs were improvements of the normal planar design of the device, such as SOI and ultrathin body devices. In so-called FinFET structures, current flows through a thin silicon fin and is controlled by two gates in parallel on both sides of the fin. Vertical MOSFET devices represent a new category. In these structures the planar arrangement of the source gate and drain is turned through 90° so that they are positioned on top of each other and the current flow is perpendicular to the surface. By utilizing the 3rd dimension, the channel length can be adjusted by layer deposition and thus dispensing with advanced (and expensive) lithography. Furthermore, depending on the application, the vertical designs require less space than planar ones so that it is possible to increase integration density. The present paper gives a review of vertical MOSFET devices with current flow perpendicular to the surface. PACS 85.30     

Quantum Boltzmann equation solved by Monte Carlo method for nano-scale semiconductor devices simulation

A two-dimensional (2D) full band self-consistent ensemble Monte Carlo (MC) method for solving the quantum Boltzmann equation, including collision broadening and quantum potential corrections, is developed to extend the MC method to the study of nano-scale semiconductor devices with obvious quantum mechanical (QM) effects. The quantum effects both in real space and momentum space in nano-scale semiconductor devices can be simulated. The effective mobility in the inversion layer of n and p channel MOSFET is simulated and compared with experimental data to verify this method. With this method 50nm ultra thin body silicon on insulator MOSFET are simulated. Results indicate that this method can be used to simulate the 2D QM effects in semiconductor devices including tunnelling effect.     

Optical effects on the characteristics of a nanoscale SOI MOSFET with uniform doping profile

This paper deals with the effects of optical radiation on a uniformly doped three dimensional nano scale SOI MOSFET including quantum mechanical effects. The model takes into account all the major effects that determine the device characteristics in the illuminated condition. The device characteristics are obtained using self-consistent solution of 3D Poisson–Schrodinger equations using Leibman's iteration method. Calculations were carried out to examine the effect of illumination on the surface potential, current–voltage characteristics, drain to source resistance (R_ds), sub threshold characteristics and transconductance (g_m). The obtained characteristics are used to examine the performance of the device for its suitable use as a photodetector in opto-electronic integrated circuit (OEIC) receivers.     

A compact program code for simulations of quantum algorithms in classical computers

A general quantum simulation language on a classical computer provides the opportunity to compare an experiential result from the development of quantum computers with mathematical theory. The intention of this research is to develop a program language that is able to make simulations of all quantum algorithms in same framework. This study examines the simulation of quantum algorithms on a classical computer with a symbolic programming language. We use the language Mathematica to make simulations of well-known quantum algorithms. The program code implemented on a classical computer will be a straight connection between the mathematical formulation of quantum mechanics and computational methods. This gives us an uncomplicated and clear language for the implementations of algorithms. The computational language includes essential formulations such as quantum state, superposition and quantum operator. This symbolic programming language provides a universal framework for examining the existing as well as future quantum algorithms. This study contributes with an implementation of a quantum algorithm in a program code where the substance is applicable in other simulations of quantum algorithms.     

Effect of interface roughness on the carrier transport in germanium MOSFETs investigated by Monte Carlo method

Interface roughness strongly influences the performance of germanium metal--organic--semiconductor field effect transistors (MOSFETs). In this paper, a 2D full-band Monte Carlo simulator is used to study the impact of interface roughness scattering on electron and hole transport properties in long- and short- channel Ge MOSFETs inversion layers. The carrier effective mobility in the channel of Ge MOSFETs and the in non-equilibrium transport properties are investigated. Results show that both electron and hole mobility are strongly influenced by interface roughness scattering. The output curves for 50~nm channel-length double gate n and p Ge MOSFET show that the drive currents of n- and p-Ge MOSFETs have significant improvement compared with that of Si n- and p-MOSFETs with smooth interface between channel and gate dielectric. The $82\%$ and $96\%$ drive current enhancement are obtained for the n- and p-MOSFETs with the completely smooth interface. However, the enhancement decreases sharply with the increase of interface roughness. With the very rough interface, the drive currents of Ge MOSFETs are even less than that of Si MOSFETs. Moreover, the significant velocity overshoot also has been found in Ge MOSFETs.     

A front-tracking/ghost-fluid method for fluid interfaces in compressible flows

A front-tracking/ghost-fluid method is introduced for simulations of fluid interfaces in compressible flows. The new method captures fluid interfaces using explicit front-tracking and defines interface conditions with the ghost-fluid method. Several examples of multiphase flow simulations, including a shock–bubble interaction, the Richtmyer–Meshkov instability, the Rayleigh–Taylor instability, the collapse of an air bubble in water and the breakup of a water drop in air, using the Euler or the Navier–Stokes equations, are performed in order to demonstrate the accuracy and capability of the new method. The computational results are compared with experiments and earlier computational studies. The results show that the new method can simulate interface dynamics accurately, including the effect of surface tension. Results for compressible gas–water systems show that the new method can be used for simulations of fluid interface with large density differences.     

Fabrication and characterization of groove-gate MOSFETs based on a self-aligned CMOS process

N and P-channel groove-gate MOSFETs based on a self-aligned CMOS process have been fabricated and characterized. For the devices with channel length of 140nm, the measured drain induced barrier lowering (DIBL) was 66mV/V for n-MOSFETs and 82mV/V for p-MOSFETs. The substrate current of a groove-gate n-MOSFET was 150 times less than that of a conventional planar n-MOSFET. These results demonstrate that groove-gate MOSFETs have excellent capabilities in suppressing short-channel effects. It is worth emphasizing that our groove-gate MOSFET devices are fabricated by using a simple process flow, with the potential of fabricating devices in the sub-100nm range.     

Novel partially depleted SOI MOSFET for suppression floating-body effect: An embedded JFET structure

Silicon-on-insulator (SOI) devices have an inherent floating body effect which may cause substantial influences in the performance of SOI devices and circuits. In this paper we propose a novel device structure to suppress the floating body effect by using an embedded junction field effect transistor (JFET). The key idea in this work is to provide a path for accumulated holes to flow out of the body to improving of electrical performance. We have introduced a p⁺-Si_1−xGe_x buried region under the n⁺-Si_1−xGe_x source and called the proposed structure as embedded JFET SOI MOSFET (EJFET–SOI). Using two-dimensional two-carrier simulation, the output and subthreshold characteristics of EJFET–SOI are compared with those of conventional SOI counterparts. The simulated results show the suppression of floating body effect in the EJFET–SOI structure as expected without consuming a significant amount of area.     

SiC肖特基源漏MOSFET的阈值电压

SiC肖特基源漏MOSFET的阈值电压不同于传统的MOSFET的阈值电压.在深入分析工作机理的基础上,利用二维模拟软件ISE提取并分析了器件的阈值电压.对SiC肖特基源漏MOSFET的阈值电压给出物理描述,得出当源极载流子主要以场发射方式进入沟道,同时沟道进入强反型状态,此时的栅电压是该器件的阈值电压. 关键词： 碳化硅 肖特基接触 阈值电压     

小尺寸应变Si金属氧化物半导体场效应晶体管栅隧穿电流预测模型

小尺寸金属氧化物半导体场效应晶体管(MOSFET)器件由于具有超薄的氧化层、关态栅隧穿漏电流的存在严重地影响了器件的性能,应变硅MOSFET器件也存在同样的问题.为了说明漏电流对新型应变硅器件性能的影响,文中利用积分方法从准二维表面势分析开始,提出了小尺寸应变硅MOSFET栅隧穿电流的理论预测模型,并在此基础上使用二维器件仿真软件ISE进行了仔细的比对研究,定量分析了在不同栅压、栅氧化层厚度下MOSFET器件的性能.仿真结果很好地与理论分析相符合,为超大规模集成电路的设计提供了有价值的参考. 关键词： 应变硅 准二维表面势 栅隧穿电流 预测模型     

物理型硬件木马失效机理及检测方法

对两种物理型硬件木马造成芯片退化或失效的机理进行了详细分析. 通过使用ATLAS 二维器件仿真系统并结合SmartSpice电路逻辑仿真器, 模拟了两种物理型硬件木马对反相器逻辑电路输出特性的影响. 使用ATHENA工艺仿真系统模拟了掺杂离子注入工艺过程, 实现了掺杂型硬件木马的金属-氧化物-半导体场效应管(MOSFET)器件; 使用热载流子注入退化模型对ATLAS 仿真器件进行热载流子压力测试, 以模拟热载流子注入型硬件木马注入MOSFET器件并造成器件退化失效的过程, 分别将上述掺杂型硬件木马和热载流子注入型硬件木马的MOSFET器件与另一个正常MOSFET器件组成同样的反相器逻辑电路. 反相器使用Spice 逻辑电路仿真输出DC直流、AC瞬态传输特性以研究物理型硬件木马对电路输出特性的影响. 为了研究MOSFET器件的物理特性本身对硬件木马的影响, 在不同温度不同宽长比(W/L)下同样对反相器进行Spice电路逻辑输出仿真. 本文分析了离子掺杂工艺、热载流子注入压力测试形成的物理型硬件木马随压力强度、温度的变化对逻辑电路输出特性的影响. 通过结果对比分析得出了含有物理型硬件木马的逻辑电路在DC直流输出特性上的扰动比AC瞬态传输特性更明显的结论. 因此, 本文提出了一种针对物理型硬件木马的检测流程. 同时, 该检测流程是一种具有可操作性的检测物理型硬件木马的方法.     

A two-dimensional threshold voltage analytical model for metal-gate/high-k/SiO₂ /Si stacked MOSFETs

In this paper the influences of the metal-gate and high-k/SiO 2 /Si stacked structure on the metal-oxide-semiconductor field-effect transistor(MOSFET) are investigated.The flat-band voltage is revised by considering the influences of stacked structure and metal-semiconductor work function fluctuation.The two-dimensional Poisson’s equation of potential distribution is presented.A threshold voltage analytical model for metal-gate/high-k/SiO 2 /Si stacked MOSFETs is developed by solving these Poisson’s equations using the boundary conditions.The model is verified by a two-dimensional device simulator,which provides the basic design guidance for metal-gate/high-k/SiO 2 /Si stacked MOSFETs.     

A two-dimensional threshold voltage analytical model for metal-gate/high-k/SiO2/Si stacked MOSFETs

In this paper the influences of the metal-gate and high-k/SiO 2 /Si stacked structure on the metal-oxide-semiconductor field-effect transistor（MOSFET） are investigated.The flat-band voltage is revised by considering the influences of stacked structure and metal-semiconductor work function fluctuation.The two-dimensional Poisson＇s equation of potential distribution is presented.A threshold voltage analytical model for metal-gate/high-k/SiO 2 /Si stacked MOSFETs is developed by solving these Poisson＇s equations using the boundary conditions.The model is verified by a two-dimensional device simulator,which provides the basic design guidance for metal-gate/high-k/SiO 2 /Si stacked MOSFETs.