A new analytical model for the surface electric field distribution and breakdown voltage of the SOI trench LDMOS

A new analytical model for the surface electric field distribution and breakdown voltage of the silicon on insulator (SOI) trench lateral double-diffused metal-oxide-semiconductor (LDMOS) is presented. Based on the two-dimensional Laplace solution and Poisson solution, the model considers the influence of structure parameters such as the doping concentration of the drift region, and the depth and width of the trench on the surface electric field. Further, a simple analytical expression of the breakdown voltage is obtained, which offers an effective way to gain an optimal high voltage. All the analytical results are in good agreement with the simulation results.     

具有纵向辅助耗尽衬底层的新型横向双扩散金属氧化物半导体场效应晶体管

为了优化横向双扩散金属氧化物半导体场效应晶体管(lateral double-diffused MOSFET,LDMOS)的击穿特性及器件性能,在传统LDMOS结构的基础上,提出了一种具有纵向辅助耗尽衬底层(assisted depletesubstrate layer,ADSL)的新型LDMOS.新加入的ADSL层使得漏端下方的纵向耗尽区大幅向衬底扩展,从而利用电场调制效应在ADSL层底部引入新的电场峰,使纵向电场得到优化,同时横向表面电场也因为电场调制效应而得到了优化.通过ISE仿真表明,当传统LDMOS与ADSL LDMOS的漂移区长度都是70μm时,击穿电压由462 V增大到897 V,提高了94%左右,并且优值也从0.55 MW/cm~2提升到1.24 MW/cm~2,提升了125%.因此,新结构ADSL LDMOS的器件性能较传统LDMOS有了极大的提升.进一步对ADSL层进行分区掺杂优化,在新结构的基础上,击穿电压在双分区时上升到938 V,三分区时为947 V.     

One-dimensional breakdown voltage model of SOI RESURF lateral power device based on lateral linearly graded approximation

A novel one-dimensional(1D) analytical model is proposed for quantifying the breakdown voltage of a reduced surface field(RESURF) lateral power device fabricated on silicon on an insulator(SOI) substrate.We assume that the charges in the depletion region contribute to the lateral PN junctions along the diagonal of the area shared by the lateral and vertical depletion regions.Based on the assumption,the lateral PN junction behaves as a linearly graded junction,thus resulting in a reduced surface electric field and high breakdown voltage.Using the proposed model,the breakdown voltage as a function of device parameters is investigated and compared with the numerical simulation by the TCAD tools.The analytical results are shown to be in fair agreement with the numerical results.Finally,a new RESURF criterion is derived which offers a useful scheme to optimize the structure parameters.This simple 1D model provides a clear physical insight into the RESURF effect and a new explanation on the improvement in breakdown voltage in an SOI RESURF device.     

新型缓冲层分区电场调制横向双扩散超结功率器件

为了突破传统横向双扩散金属-氧化物-半导体器件(lateral double-diffused MOSFET)击穿电压与比导通电阻的极限关系,本文在缓冲层横向双扩散超结功率器件(super junction LDMOS-SJ LDMOS)结构基础上,提出了具有缓冲层分区新型SJ-LDMOS结构.新结构利用电场调制效应将分区缓冲层产生的电场峰引入超结(super junction)表面而优化了SJ-LDMOS的表面电场分布,缓解了横向LDMOS器件由于受纵向电场影响使横向电场分布不均匀、横向单位耐压量低的问题.利用仿真分析软件ISE分析表明,优化条件下,当缓冲层分区为3时,提出的缓冲层分区SJ-LDMOS表面电场最优,击穿电压达到饱和时较一般LDMOS结构提高了50%左右,较缓冲层SJ-LDMOS结构提高了32%左右,横向单位耐压量达到18.48 V/μm.击穿电压为382 V的缓冲层分区SJ-LDMOS,比导通电阻为25.6 mΩ·cm2,突破了一般LDMOS击穿电压为254 V时比导通电阻为71.8 mΩ·cm2的极限关系.     

Modeling of a triple reduced surface field silicon-on-insulator lateral double-diffused metal–oxide–semiconductor field-effect transistor with low on-state resistance

An analytical model for a novel triple reduced surface field(RESURF) silicon-on-insulator(SOI) lateral doublediffused metal–oxide–semiconductor(LDMOS) field effect transistor with n-type top(N-top) layer, which can obtain a low on-state resistance, is proposed in this paper. The analytical model for surface potential and electric field distributions of the novel triple RESURF SOI LDMOS is presented by solving the two-dimensional(2D) Poisson's equation, which can also be applied to single, double and conventional triple RESURF SOI structures. The breakdown voltage(BV) is formulized to quantify the breakdown characteristic. Besides, the optimal integrated charge of N-top layer(Q_(ntop)) is derived, which can give guidance for doping the N-top layer. All the analytical results are well verified by numerical simulation results,showing the validity of the presented model. Hence, the proposed model can be a good tool for the device designers to provide accurate first-order design schemes and physical insights into the high voltage triple RESURF SOI device with N-top layer.     

A High Performance Silicon-on-Insulator LDMOSTT Using Linearly Increasing Thickness Techniques

We present a new technique to achieve uniform lateral electric field and maximum breakdown voltage in lateral double-diffused metal-oxide-semiconductor transistors fabricated on silicon-on-insulator substrates. A linearly increasing drift-region thickness from the source to the drain is employed to improve the electric field distribution in the devices. Compared to the lateral linear doping technique and the reduced surface field technique, twodimensional numerical simulations show that the new device exhibits reduced specific on-resistance, maximum off- and on-state breakdown voltages, superior quasi-saturation characteristics and improved safe operating area.     

A novel thin drift region device with field limiting rings in substrate

A novel thin drift region device with heavily doped N⁺ rings embedded in the substrate is reported, which is called the field limiting rings in substrate lateral double-diffused MOS transistor (SFLR LDMOS). In the SFLR LDMOS, the peak of the electric field at the main junction is reduced due to the transfer of the voltage from the main junction to other field limiting ring junctions, so the vertical electric field is improved significantly. A model of the breakdown voltage is developed, from which optimal spacing is obtained. The numerical results indicate that the breakdown voltage of the device proposed is increased by 76% in comparison to that of the conventional LDMOS.     

漂移区表面阶梯掺杂LDMOS的击穿电压模型

提出表面阶梯掺杂(SD：Step Doping on surface)LDMOS的二维击穿电压模型.基于求解多区二维Poisson方程,获得SD结构表面电场的解析式.借助此模型,研究其结构参数对击穿电压的影响;计算优化漂移区浓度和厚度与结构参数的关系,给出获得最大击穿电压的途径.数值结果,解析结果和试验结果符合较好.漂移区各区和衬底电场相互调制,在漂移区中部产生新的峰值,改善电场分布;高掺杂区位于表面,降低了正向导通电阻.结果表明：SD结构较常规结构击穿电压从192V提高到242V,导通电阻下降33%. 关键词： 阶梯掺杂 模型 优化 调制     

Numerical and analytical investigations for the SOI LDMOS with alternated high-k dielectric and step doped silicon pillars

This paper presents a new silicon-on-insulator(SOI) lateral-double-diffused metal-oxide-semiconductor transistor(LDMOST) device with alternated high-k dielectric and step doped silicon pillars(HKSD device). Due to the modulation of step doping technology and high-k dielectric on the electric field and doped profile of each zone, the HKSD device shows a greater performance. The analytical models of the potential, electric field, optimal breakdown voltage, and optimal doped profile are derived. The analytical results and the simulated results are basically consistent, which confirms the proposed model suitable for the HKSD device. The potential and electric field modulation mechanism are investigated based on the simulation and analytical models. Furthermore, the influence of the parameters on the breakdown voltage(BV) and specific on-resistance(R_on,sp) are obtained. The results indicate that the HKSD device has a higher BV and lower R_on,sp compared to the SD device and HK device.     

A uniform doping ultra-thin SOI LDMOS with accumulation-mode extended gate and back-side etching technology

A uniform doping ultra-thin silicon-on-insulator(SOI) lateral-double-diffused metal-oxide-semiconductor(LDMOS)with low specific on-resistance(R_on,sp) and high breakdown voltage(BV) is proposed and its mechanism is investigated.The proposed LDMOS features an accumulation-mode extended gate(AG) and back-side etching(BE). The extended gate consists of a P– region and two diodes in series. In the on-state with VGD 0, an electron accumulation layer is formed along the drift region surface under the AG. It provides an ultra-low resistance current path along the whole drift region surface and thus the novel device obtains a low temperature distribution. The R_on,sp is nearly independent of the doping concentration of the drift region. In the off-state, the AG not only modulates the surface electric field distribution and improves the BV, but also brings in a charge compensation effect to further reduce the R_on,sp. Moreover, the BE avoids vertical premature breakdown to obtain high BV and allows a uniform doping in the drift region, which avoids the variable lateral doping(VLD) and the "hot-spot" caused by the VLD. Compared with the VLD SOI LDMOS, the proposed device simultaneously reduces the R_on,sp by 70.2% and increases the BV from 776 V to 818 V.     

The breakdown mechanism of a high-side pLDMOS based on a thin-layer silicon-on-insulator structure

A high-side thin-layer silicon-on-insulator (SOI) pLDMOS is proposed, adopting field implant (FI) and multiple field plate (MFP) technologies. The breakdown mechanisms of back gate (BG) turn-on, surface channel punch-through, and vertical and lateral avalanche breakdown are investigated by setting up analytical models, simulating related parameters and verifying experimentally. The device structure is optimized based on the above research. The shallow junction achieved through FI technology attenuates the BG effect, the optimized channel length eliminates the surface channel punch-through, the advised thickness of the buried oxide dispels the vertical avalanche breakdown, and the MFP technology avoids premature lateral avalanche breakdown by modulating the electric field distribution. Finally, for the first time, a 300 V high-side pLDMOS is experimentally realized on a 1.5 μ m thick thin-layer SOI.     

A new analytical model of high voltage silicon on insulator （SOI） thin film devices

A new analytical model of high voltage silicon on insulator (SOI) thin film devices is proposed, and a formula of silicon critical electric field is derived as a function of silicon film thickness by solving a 2D Poisson equation from an effective ionization rate, with a threshold energy taken into account for electron multiplying. Unlike a conventional silicon critical electric field that is constant and independent of silicon film thickness, the proposed silicon critical electric field increases sharply with silicon film thickness decreasing especially in the case of thin films, and can come to 141V/μm at a film thickness of 0.1μm which is much larger than the normal value of about 30V/μm. From the proposed formula of silicon critical electric field, the expressions of dielectric layer electric field and vertical breakdown voltage (V_B,V) are obtained. Based on the model, an ultra thin film can be used to enhance dielectric layer electric field and so increase vertical breakdown voltage for SOI devices because of its high silicon critical electric field, and with a dielectric layer thickness of 2μm the vertical breakdown voltages reach 852 and 300V for the silicon film thicknesses of 0.1 and 5μm, respectively. In addition, a relation between dielectric layer thickness and silicon film thickness is obtained, indicating a minimum vertical breakdown voltage that should be avoided when an SOI device is designed. 2D simulated results and some experimental results are in good agreement with analytical results.     

电荷非平衡super junction结构电场分布

建立了电荷非平衡情况下super junction(SJ)耐压结构的二维电场分布理论模型. 获得了浓度和宽度非平衡、梯形n-/p- 区和横向线性缓变掺杂三种非平衡SJ结构的电场分布. 理论分析结果与二维器件数值仿真软件MEDICI的仿真结果符合良好. 虽然给出的电场分布为三角级数形式, 但仍能从中获得很多重要信息. 特别地, 由此可求出非平衡SJ结构的峰值电场和耐压. 该结果有助于对SJ结构的深入分析. 关键词： super junction 电场分布 电荷非平衡     

New CMOS compatible super junction LDMOST with n-type buried layer

A new super-junction lateral double diffused MOSFET (LDMOST) structure is designed with n-type charge compensation layer embedded in the p$^{ - }$-substrate near the drain to suppress substrate-assisted depletion effect that results from the compensating charges imbalance between the pillars in the n-type buried layer. A high electric field peak is introduced in the surface by the pn junction between the p$^{ - }$-substrate and n-type buried layer, which given rise to a more uniform surface electric field distribution by modulation effect. The effect of reduced bulk field (REBULF) is introduced to improve the vertical breakdown voltage by reducing the high bulk electric field around the drain. The new structure features high breakdown voltage, low on-resistance and charges balance in the drift region due to n-type buried layer.     

具有半绝缘多晶硅完全三维超结横向功率器件

为了突破传统LDMOS (lateral double-diffused MOSFET)器件击穿电压与比导通电阻的硅极限的2.5 次方关系, 降低LDMOS器件的功率损耗, 提高功率集成电路的功率驱动能力, 提出了一种具有半绝缘多晶硅SIPOS (semi-insulating poly silicon)覆盖的完全3 D-RESURF (three-dimensional reduced surface field)新型Super Junction-LDMOS结构(SIPOS SJ-LDMOS). 这种结构利用SIPOS的电场调制作用使SJ-LDMOS的表面电场分布均匀, 将器件单位长度的耐压量提高到19.4 V/μupm; 覆盖于漂移区表面的SIPOS使SJ-LDMOS沿三维方向均受到电场调制, 实现了LDMOS的完全3 D-RESURF效应, 使更高浓度的漂移区完全耗尽而达到高的击穿电压; 当器件开态工作时, 覆盖于薄场氧化层表面的SIPOS的电场作用使SJ-LDMOS的漂移区表面形成多数载流子积累, 器件比导通电阻降低. 利用器件仿真软件ISE分析获得, 当SIPOS SJ-LDMOS的击穿电压为388 V时, 比导通电阻为20.87 mΩ·cm², 相同结构参数条件下, N-buffer SJ-LDMOS的击穿电压为287 V, 比导通电阻为31.14 mΩ·cm²; 一般SJ-LDMOS 的击穿电压仅为180 V, 比导通电阻为71.82 mΩ·cm².     

A novel LDMOS with a junction field plate and a partial N-buried layer

A novel lateral double-diffused metal–oxide semiconductor (LDMOS) with a high breakdown voltage (BV) and low specific on-resistance (R_on.sp) is proposed and investigated by simulation. It features a junction field plate (JFP) over the drift region and a partial N-buried layer (PNB) in the P-substrate. The JFP not only smoothes the surface electric field (E-field), but also brings in charge compensation between the JFP and the N-drift region, which increases the doping concentration of the N-drift region. The PNB reshapes the equipotential contours, and thus reduces the E-field peak on the drain side and increases that on the source side. Moreover, the PNB extends the depletion width in the substrate by introducing an additional vertical diode, resulting in a significant improvement on the vertical BV. Compared with the conventional LDMOS with the same dimensional parameters, the novel LDMOS has an increase in BV value by 67.4%, and a reduction in R_on.sp by 45.7% simultaneously.     

Breakdown voltage analysis of Al0.25Ga0.75N/GaN high electron mobility transistors with partial silicon doping in the AlGaN layer

In this paper,two-dimensional electron gas（2DEG） regions in AlGaN/GaN high electron mobility transistors（HEMTs） are realized by doping partial silicon into the AlGaN layer for the first time.A new electric field peak is introduced along the interface between the AlGaN and GaN buffer by the electric field modulation effect due to partial silicon positive charge.The high electric field near the gate for the complete silicon doping structure is effectively decreased,which makes the surface electric field uniform.The high electric field peak near the drain results from the potential difference between the surface and the depletion regions.Simulated breakdown curves that are the same as the test results are obtained for the first time by introducing an acceptor-like trap into the N-type GaN buffer.The proposed structure with partial silicon doping is better than the structure with complete silicon doping and conventional structures with the electric field plate near the drain.The breakdown voltage is improved from 296 V for the conventional structure to 400 V for the proposed one resulting from the uniform surface electric field.     

Breakdown voltage analysis of Al_0.25Ga_0.75N/GaN high electron mobility transistors with partial silicon doping in the AlGaN layer

In this paper,two-dimensional electron gas(2DEG) regions in AlGaN/GaN high electron mobility transistors(HEMTs) are realized by doping partial silicon into the AlGaN layer for the first time.A new electric field peak is introduced along the interface between the AlGaN and GaN buffer by the electric field modulation effect due to partial silicon positive charge.The high electric field near the gate for the complete silicon doping structure is effectively decreased,which makes the surface electric field uniform.The high electric field peak near the drain results from the potential difference between the surface and the depletion regions.Simulated breakdown curves that are the same as the test results are obtained for the first time by introducing an acceptor-like trap into the N-type GaN buffer.The proposed structure with partial silicon doping is better than the structure with complete silicon doping and conventional structures with the electric field plate near the drain.The breakdown voltage is improved from 296 V for the conventional structure to 400 V for the proposed one resulting from the uniform surface electric field.     

Control of electric field in 4H-SiC UMOSFET: Physical investigation

In this paper, we show how breakdown voltage (V_BR) and the specific on-resistance (R_on) can be improved simply by controlling of the electric field in a power 4H-SiC UMOSFET. The key idea in this work is increasing the uniformity of the electric field profile by inserting a region with a graded doping density (GD region) in the drift region. The doping density of inserted region is decreased gradually from top to bottom, called Graded Doping Region UMOSFET (GDR-UMOSFET). The GD region results in a more uniform electric field profile in comparison with a conventional UMOSFET (C-UMOSFET) and a UMOSFET with an accumulation layer (AL-UMOSFET). This in turn improves breakdown voltage. Using two-dimensional two-carrier simulation, we demonstrate that the GDR-UMOSFET shows higher breakdown voltage and lower specific on-resistance. Our results show the maximum breakdown voltage of 1340 V is obtained for the GDR-UMOSFET with 10 µm drift region length, while at the same drift region length and approximated doping density, the maximum breakdown voltages of the C-UMOSFET and the AL-UMOSFET structures are 534 V and 703 V, respectively.     

Experimental and numerical analyses of high voltage 4H-SiC junction barrier Schottky rectifiers with linearly graded field limiting ring

This paper describes the successful fabrication of 4H-SiC junction barrier Schottky(JBS) rectifiers with a linearly graded field limiting ring(LG-FLR). Linearly variable ring spacings for the FLR termination are applied to improve the blocking voltage by reducing the peak surface electric field at the edge termination region, which acts like a variable lateral doping profile resulting in a gradual field distribution. The experimental results demonstrate a breakdown voltage of 5 kV at the reverse leakage current density of 2 mA/cm2(about 80% of the theoretical value). Detailed numerical simulations show that the proposed termination structure provides a uniform electric field profile compared to the conventional FLR termination, which is responsible for 45% improvement in the reverse blocking voltage despite a 3.7% longer total termination length.