Fin width and height dependence of bipolar amplification in bulk FinFETs submitted to heavy ion irradiation

Fin FET technologies are becoming the mainstream process as technology scales down. Based on a 28-nm bulk pFin FET device, we have investigated the fin width and height dependence of bipolar amplification for heavy-ion-irradiated Fin FETs by 3D TCAD numerical simulation. Simulation results show that due to a well bipolar conduction mechanism rather than a channel(fin) conduction path, the transistors with narrower fins exhibit a diminished bipolar amplification effect, while the fin height presents a trivial effect on the bipolar amplification and charge collection. The results also indicate that the single event transient(SET) pulse width can be mitigated about 35% at least by optimizing the ratio of fin width and height, which can provide guidance for radiation-hardened applications in bulk Fin FET technology.     

Effect of supply voltage and body-biasing on single-event transient pulse quenching in bulk fin field-effect-transistor process

Charge sharing is becoming an important topic as the feature size scales down in fin field-effect-transistor(Fin FET)technology. However, the studies of charge sharing induced single-event transient(SET) pulse quenching with bulk Fin FET are reported seldomly. Using three-dimensional technology computer aided design(3DTCAD) mixed-mode simulations,the effects of supply voltage and body-biasing on SET pulse quenching are investigated for the first time in bulk Fin FET process. Research results indicate that due to an enhanced charge sharing effect, the propagating SET pulse width decreases with reducing supply voltage. Moreover, compared with reverse body-biasing(RBB), the circuit with forward body-biasing(FBB) is vulnerable to charge sharing and can effectively mitigate the propagating SET pulse width up to 53% at least.This can provide guidance for radiation-hardened bulk Fin FET technology especially in low power and high performance applications.     

A novel nanoscale fin field effect transistor by amended channel: Investigation and fundamental physics

The present paper proposes a new Fin Field Effect Transistor (FinFET) with an amended Channel (AC). The fin region consists of two sections; the lower part which has a rounded shape and the upper part of fin as conventional FinFETs, is cubic. The AC-FinFET devices are proven to have a lower threshold voltage roll-off, reduced DIBL, better subthreshold slope characteristics, and a better gate capacitance in comparison with the C-FinFET. Moreover, the simulation result with three-dimensional and two-carrier device simulator demonstrates an improved output characteristic of the proposed structure due to reduction of self-heating effect. Due to the rounded shape of the lower fin region and decreasing corner effects there, the heat can flow easily, and the device temperature will decrease. Also the gate control over the channel increases due to the narrow upper part of the fin. The paper, thus, attempts to show the advantages of higher performance AC-FinFET device over the conventional one, and its effect on the operation of nanoscale devices.     

Static dielectric constant assessment from capacitance over a wide range of electrode separations

Static dielectric constant extraction from two-electrode capacitance measurement over a wide range of electrode separations and dielectric constants involves careful assessment of fringe fields. Finite-element method has been employed to compute capacitance and quantify fringe fields for parallel electrode capacitor of (finite thickness, radii r, electrode separation d), with a homogeneous dielectric medium extending up to the geometric limits of the electrodes. Two distinct regimes, in the fringe field contributions are seen. A procedure to extract the static dielectric constant has been proposed for the first regime and a validation has been provided for the same.     

An analytical model for nanowire junctionless SOI Fin FETs with considering three-dimensional coupling effect

In this paper, the three-dimensional(3D) coupling effect is discussed for nanowire junctionless silicon-on-insulator(SOI) Fin FETs. With fin width decreasing from 100 nm to 7 nm, the electric field induced by the lateral gates increases and therefore the influence of back gate on the threshold voltage weakens. For a narrow and tall fin, the lateral gates mainly control the channel and therefore the effect of back gate decreases. A simple two-dimensional(2D) potential model is proposed for the subthreshold region of junctionless SOI Fin FET. TCAD simulations validate our model. It can be used to extract the threshold voltage and doping concentration. In addition, the tuning of back gate on the threshold voltage can be predicted.     

A proposed ultra low-noise optical receiver for 1.55 μm applications

A high-sensitivity optical receiver based on InP/InGaAs superlattice avalanche photodiode (SL-APD) followed by an InGaAs MESFET transimpedance pre-amplifier has been proposed for operation in 1.55 m wavelength region. The proposed optical receiver may be realised in the hybrid integrated circuit form. The low excess-noise factor of the SL-APD significantly reduces the value of minimum detectable optical power and improves the sensitivity of the over all receiver. The proposed receiver has been analysed theoretically. The results of computation show that the device has a high transimpedance gain (60 dB-ohm) with a bandwidth of 11 GHz for a photodetector capacitance of 110 fF. The sensitivity of the receiver has been found to be (–27.3d Bm) at operating bit rate of 15 Gb/s for a bit-error-rate of 10^–9. The performance of the receiver can be optimised in respect of transimpedance gain, bandwidth and sensitivity by following guidelines provided in this paper. The proposed photoreceiver outperforms the existing receivers based on p-i-n/FET or conventional APD/FET photoreceivers.     

GaN HEMT栅边缘电容用于缺陷的研究

本文对GaN HEMT栅漏电容的频率色散特性进行分析,认为栅边缘电容的色散是导致栅漏电容频率色散特性不同于圆肖特基二极管电容的主要原因. 通过对不同栅偏置条件下缺陷附加电容与频率关系的拟合,发现小栅压下的缺陷附加电容仅满足单能级缺陷模型,而强反向栅压下的缺陷附加电容同时满足单能级和连续能级缺陷模型. 实验中栅边缘电容的频率色散现象在钝化工艺后出现,其反映的缺陷很可能是钝化工艺引入,且位于源漏间栅金属未覆盖区域的表面. 最后通过低频噪声技术进一步验证栅边缘电容提取缺陷参数的可行性. 低频噪声技术获得的单能级 关键词： HEMT 边缘电容 缺陷 低频噪声     

Low-parasitic ESD protection strategy for RF ICs in 0.35μm CMOS process

A systemic and comprehensive ESD-induced parasitic model is presented in this paper, which is used to analyse the parasitic influences of electrostatic discharge (ESD) protection circuits on the performance of radio frequency applications. A novel low-parasitic ESD protection structure is made in a 0.35\mum 1P3M silicide CMOS process. The measured results show that this novel structure has a low parasitic capacitance about 310fF and a low leakage current about 12.2nA with a suitable ESD robustness target about 5kV human body model.     

A new nanoscale and high temperature field effect transistor: Bi level FinFET

In this paper, we propose a new Bi Level Fin Field Effect Transistor (BL-FinFET) where the fin regions consist of Bi level. The novel features of the BL-FinFET are simulated and compared with a Conventional FinFET (C-FinFET). The three-dimensional and two-carrier device simulation demonstrate that the application of Bi level to the FinFET structure results in an ideal threshold voltage roll-off, reduced DIBL, excellent behavior in voltage gain at high temperatures and the gate capacitance improvement when compared with the C-FinFET. Also, this paper illustrates the benefits of the high performance BL-FinFET device over the conventional one and expands the application of Silicon on Insulator Metal Oxide Semiconductor Field Effect Transistors (SOI MOSFETs) to high temperature.     

一种新的反向投影条纹生成方法研究

反向条纹投影技术是一种应用于在线或批量检测的快速而稳定的光学三维面形检测技术.提出了一种新的产生反向条纹的算法,新的算法建立投影器坐标系与摄像机坐标系的正向映射变换关系,通过投影器坐标系上一个像素点的两套相位值,找到其在摄像机坐标系中对应的位置,即产生投影器坐标系像素点在摄像机坐标系中的注册.由于期望在摄像机中观察到的条纹图像只是简单的正弦条纹图像,直接读取注册点的期望条纹相位,很容易产生反向条纹.计箅机模拟和反向条纹投影实验中的相位标准差分别达到7.044×10-6 rad和3.34×10-2rad,比以前的方法在精度上有了较大的提高,并简要分析了精度提高的原因.计算机模拟和实物测试实验都验证了该方法的可行性.     

应变Si n型金属氧化物半导体场效应晶体管电荷模型

基于应变Si/SiGe器件结构,本文建立了统一的应变Si NMOSFET电荷模型.该模型采用电荷作为状态变量,解决了电荷守恒问题.同时采用平滑函数,实现了应变Si NMOSFET端口电荷及其电容,从亚阈值区到强反型区以及从线性区到饱和区的平滑性,解决了模型的连续性问题.然后采用模拟硬件描述语言Verilog-A建立了电容模型.通过将模型的仿真结果和实验结果对比分析,验证了所建模型的有效性.该模型可为应变Si集成电路分析、设计提供重要参考.     

The impact of ground plane size upon the performance of Field-induced Charged Device Model ESD testing systems

Experimental measurements of peak stressing current in a laboratory prototype Field-induced Charged Device Model (FCDM) ESD testing system have revealed a nonlinear dependence upon ground plane area and test module capacitance. This dependence is explained by an expanded equivalent circuit model for the testing system that takes explicit account of the parasitic capacitance between the ground plane on the test head and the underlying field plate. The results of this work underscore the importance of ensuring that the ground plane is sufficiently large to cover the device under test.     

Ultrafast characterization of in-plane-gate field-effect transistors: parasitics in laterally gated transistors

In-plane-gate field-effect transistors are probed by femtosecond electrooptic sampling. Ultrafast response of the transistors is dominated by a displacement current induced by parasitic gate-drain capacitance. Intrinsic and parasitic gate-drain capacitances of various transistor structures are obtained from displacement-current characteristics and are in quantitative agreement with the calculation of planar capacitances. Intrinsic gate-drain capacitances are in the order of 100 aF, while parasitic gate-drain capacitances are between 1.7 and 4.8 fF, more than ten times that of intrinsic gate-drain capacitances. Reduction in parasitic capacitance by a factor of two is achieved by means of grounded shields and is confirmed by calculation. The grounded-shields screen parasitic electric fields and transform parasitic coupling into a part of the waveguide coupling. This reduction in parasitic capacitance is the first demonstration that the parasitic field effect is controlled artificially by nanometre-scale device technology.     

Analysis on 3D object measurement based on fringe projection

A coordinate measuring method is presented, which is specially devised to perform the measurement of coordinates with projected fringe techniques of projectors in three dimensions. The system is composed of two parts: one is a target which can move freely in three dimensions, and the other is a stationary two-dimensional array of photodetectors. The mini-projector is tied to the target, and the projected fringe is monitored by the photodetectors. The phase of the photodetectors can be precisely measured with the phase-shifting algorithm, so that, the xyz location of the target can be determined with the geometric model of multilateration using the method of optimization. In this paper, the measuring principle, iterative method, computer simulation and preliminary results are given. The phase-shifting technique has the advantages of high accuracy and noise endurance. The method will provide the basis for follow-up iterative optimization calculation. The experimental results prove that the proposed coordinate measuring method is of high precision.     

PIN光电探测器的建模与仿真分析

为了优化PIN光电探测器响应特性,首先依据载流子速率方程,并考虑芯片寄生参量和封装寄生参量,建立光电探测器的等效电路模型。然后仿真分析了反偏电压、I区宽度、光敏面、芯片寄生电阻和电容、封装寄生电阻、电容和电感对光电探测器脉冲响应特性和频率响应特性的影响。结果表明:通过增大反偏电压,减小光敏面和寄生参量(芯片寄生电容和电阻,封装寄生电容和电阻),选取合适的I区宽度,利用引线电感的谐振效应现象,可以抑制脉冲响应波形畸变,提高频率响应带宽。     

大尺寸金属氧化物TFT面板设计分析

根据最基本的2T1C像素电路,建立了TFT各参数与AMOLED面板限制因素的计算模型。详细分析了AMOLED显示尺寸与TFT迁移率、金属方块电阻、刷新频率以及器件结构的关系。在大尺寸高分辨率AMOLED面板设计中,信号线RC延迟是主要限制因素。TFT迁移率的提高在一定范围内对大尺寸显示面板设计有利,降低RC延迟是实现大尺寸、高分辨率、高刷新频率显示的关键技术。开发铜布线技术和低寄生电容TFT器件结构是未来大尺寸AMOLED显示的关键技术。     

A flexible new three-dimensional measurement technique by projected fringe pattern

Aimed at the problems of inferior precision and bad maneuverability for three-dimensional (3D) measurement by projected fringe pattern, a flexible new 3D technique for performing system calibration and measuring was proposed. First, we analyzed the principle of conventional 3D measurement with projected fringe pattern, and pointed out the shortcoming of measurement system. Then, the CCD camera calibration technique is analyzed and we set up the perspective projection model which transforms the computer image coordinate to 3D world coordinate, and we get the coordinate of the CCD camera image lens. Third, the position of projection lens optical center can be obtained using the above model. At last, some experiment results presented show that this technique is more simple and robust in engineering than conventional measurement method.     

4H-SiC 射频MESFET中陷阱参数的提取方法

针对4H-SiC 射频MESFET中的陷阱效应,采用解析的方法建立陷阱模型,分析了陷阱效应对器件带来的影响,阐述了陷阱的陷落-发射机理,提取了时间常数、陷阱浓度等相关参数.得到的模拟结果能够较好的反映实验结果. 关键词： 碳化硅 深能级陷阱 频率偏移     

Recent progress on integrating two-dimensional materials with ferroelectrics for memory devices and photodetectors

Two-dimensional(2D) materials, such as graphene and Mo S2 related transition metal dichalcogenides(TMDC), have attracted much attention for their potential applications. Ferroelectrics, one of the special and traditional dielectric materials,possess a spontaneous electric polarization that can be reversed by the application of an external electric field. In recent years, a new type of device, combining 2D materials with ferroelectrics, has been fabricated. Many novel devices have been fabricated, such as low power consumption memory devices, highly sensitive photo-transistors, etc. using this technique of hybrid systems incorporating ferroelectrics and 2D materials. This paper reviews two types of devices based on field effect transistor(FET) structures with ferroelectric gate dielectric construction(termed Fe FET). One type of device is for logic applications, such as a graphene and TMDC Fe FET for fabricating memory units. Another device is for optoelectric applications, such as high performance phototransistors using a graphene p-n junction. Finally, we discuss the prospects for future applications of 2D material Fe FET.     

忆阻器单阻态下的记忆电容行为及多态特性

采用供体-受体类型的共聚物构建了Al/共聚物/ITO结构的有机记忆器件,并对其电流-电压(I-V)和电容-电压(C-V)特性进行了研究.结果表明:器件不仅表现出明显的记忆电阻特征,而且在单个电阻状态下还存在记忆电容行为,使器件呈现出两种电阻状态和与之对应的四种电容状态,具有电阻和电容的双参量记忆能力.在此基础上对器件的电容开关行为进行了电压幅值的调制,使器件出现了更多的电容状态,为多级存储的实现提供了一条有效途径.最后通过引入分子内部极化算符,建立了记忆电阻和记忆电容的关联性,给出了描述器件双参量多状态特征的矩阵模型.