Weak-link bi-epitaxial Josephson junctions in a YBa2Cu3O7−δ film on BaZrO3/CeO2/SrTiO3

A bi-epitaxial (001)YBa₂Cu₃O_7−δ /(110)BaZrO₃/(001)CeO₂ three-layer heterostructure has been grown on (100)SrTiO₃ by laser ablation. The epitaxial relations between the layers making up the heterostructure were derived from x-ray diffraction data. The I _cR_n product for the bi-epitaxial Josephson junctions thus obtained was within 1–1.5 mV for 4.2 K, and 30–60 μV for 77 K. The normal resistance R _n=(2–5 Ω) was practically independent of temperature. The magnetic field dependences of I _c had typically a clearly pronounced main maximum, followed by distorted subsequent peaks. Interaction of the Josephson ac current with self-induced electromagnetic waves at the 45° grain boundary and with external microwave radiation (f=11 GHz) produced current steps in the I-V characteristics of the bi-epitaxial junctions at the corresponding voltages. Fiz. Tverd. Tela (St. Petersburg) 39, 1732–1738 (October 1997)     

栅漏间表面外延层对4H-SiC功率MESFET击穿 特性的改善机理与结构优化

本文提出了一种带栅漏间表面p型外延层的新型MESFET结构并整合了能精确描述4H-SiC MESFET工作机理的数值模型,模型综合考虑了高场载流子饱和、雪崩碰撞离化以及电场调制等效应. 利用所建模型分析了表面外延层对器件沟道表面电场分布的改善作用,并采用突变结近似法对p型外延层参数与器件输出电流(I_ds)和击穿电压(V_B)的关系进行了研究.结果表明,通过在常规MESFET漏端处引入新的电场峰来降低栅极边缘的强电场峰并在栅漏之间的沟道表面引入p-n结内建电场进一步降低电场峰值,改善了表面电场沿电流方向的分布.通过与常规结构以及场板结构SiC MESFET的特性对比表明,本文提出的结构可以明显改善SiC MESFET的功率特性.此外,针对文中给定的器件结构,获得了优化的设计方案,选择p型外延层厚度为0.12 μupm,掺杂浓度为5× 10¹⁵ cm^-3,可使器件的V_B提高33%而保持I_ds基本不变.     

LiNbO3晶体中屏蔽光伏孤子自偏转的 时空演化与可控因素

基于带输运模型理论建立了 LiNbO₃ 晶体屏蔽光伏孤子的时空演化动力学方程, 用有限差分方法求解发现, LiNbO₃ 晶体中明、暗屏蔽光伏孤子存在大的自偏转, 并且光孤子形状变得具有不对称性, 偏转方向的曲线斜率绝对值变大, 偏转反方向的曲线斜率绝对值变小. 分析研究表明影响其自偏转度和形变的因素包括受主浓度 N_A, 暗辐射强度 I_d 和外加电场 E₀ . 其他条件不变的情况下N_A 越大, 明孤子的自偏转度与形变越小, 暗孤子的自偏转度与形变反而越大; 对于 I_d , 它对明暗孤子的影响是相同的, I_d 越小, 晶体里诱导出的空间电荷场越容易达到饱和, 当信号光中心光强与暗辐射强度之比为 10^-1时无饱和现象产生; 随着 E₀ 数值的增大, 明孤子的自偏转度和形变减小, 而暗孤子的自偏转度和形变反而增大.     

I–V characteristics and the electric-field effect in melt-grown YBa2Cu3Ox/Y2BaCuO5 HTSC crystals

The effect of an electric field E=120 MV/m in the electrode-insulator-superconductor system on I–V curves obtained at 77 K on two types of single-crystal samples cut from monolithic superconducting YBa₂Cu₃O_x/Y₂BaCuO₅ has been studied. The Y211 nonsuperconducting phase in the ingot was in the form of precipitates ≈1 μm in size. It has been found that an electric field applied to samples with a comparatively low Y211 content (volume fraction 8%) does not affect the critical current I _c while reducing the resistance R at currents slightly above I _c . In samples containing more than 35% Y211 phase, electric field results in an increase of I _c and a decrease of R for I>I _c . Data on the critical temperature T _c and the temperature dependence of I _c have also been obtained. __________ Translated from Fizika Tverdogo Tela, Vol. 42, No. 7, 2000, pp. 1172–1175. Original Russian Text Copyright ? 2000 by Smirnov, Orlova, Sengupta, Goretta.     

Degradation of the transconductance of gate-modulated generation current in nMOSFET

The degradation of transconductance (G) of gate-modulated generation current I_GD in LDD nMOSFET is investigated. The G curve shifts rightward under the single electron-injection-stress (EIS). The trapped electrons located in the gate oxide over the LDD region (Q_L) makes the effective drain voltage minish. Accordingly, the G peak in depletion (G_MD) and that in weak inversion (G_MW) decrease. It is found that Δ G_MD and Δ G_MW each have a linear relationship with the n-th power of stress time (tⁿ) in dual-log coordinate: Δ G_MD ∝ tⁿ, Δ G_MD ∝ tⁿ (n=0.25). During the alternate stress, the injected holes neutralize Q_L induced by the previous EIS. This neutralization makes the effective V_D restore to the initial value and then the I_GD peak recovers completely. Yet the threshold voltage recovery is incomplete due to the trapped electron located over the channel (Q_C). As a result, G_MW only recovers to the circa 50% of the initial value after the hole-injection-stress (HIS). Instead, G_MD is almost recovered. The relevant mechanisms are given in detail.     

相干和非相干合成光束对金属瑞利粒子的光学俘获

研究了两光束的合成方式(相干和非相干合成)对俘获金属瑞利粒子的辐射力和稳定性的影响,着重研究了辐射力与合成方式、离轴距离、相干参数和粒子半径的关系.结果表明,不同合成方式下,离轴距离和相干参数都分别存在临界值d_c和α_c,在0d_c或α>α_c时,焦面处光强呈中心凹陷分布,此时横向梯度力不能作为回复力俘获金属瑞利粒子.在0<d≤d_c时,与非相干合成光束比较,相干合成光束在焦面处光强、辐射力、俘获刚性和纵向俘获范围更大.因此,适当选择合成方式,较小离轴距离和较低相干参数可有利于合成光束对金属瑞利粒子的俘获.     

流体静压力对高简并砷化镓P-N结某些参数的影响

本文报导了在流体静压力18000kg/cm²范围内,高简并砷化镓P-N结峯值电流l_p,谷值电流l_v,峯值电压V_p,谷值电压V_v,指数过剩电流I_x等参数随压力变化的实验结果。分析了峯值电压V_p随压力P的增加按指数规律显著减小,以及指数过剩电流I_x的斜率S=(dlnI_x)/dV随压力P的增加而增加等实验结果。分析的     

ErP5O14非晶玻璃的红外量子剪裁

研究了Er_1.0P₅O₁₄铒非晶玻璃的红外量子剪裁现象. 从吸收谱和激发光谱的计算比较中肯定了Er_1.0P₅O₁₄非晶 玻璃的1537.0 nm红外荧光为多光子量子剪裁荧光. 从Er_1.0P₅O₁₄非晶玻璃的可见和红外荧光发射光谱中发现激发²H_11/2, ⁴G_11/2和⁴G_9/2能级所导致的⁴I_13/2→⁴I_15/2量子剪裁红外荧光很强;基于自发辐射速率、无辐射弛豫速率和能量传递速率等参数的计算,对其量子剪裁机理进行了分析.发现起源于基态的强下转换能量传递{²H_11/2→⁴I_9/2,⁴I_15/2→⁴I_13/2},{⁴G_11/2→⁴I_13/2, ⁴I_15/2→²H_11/2},{⁴G_9/2→⁴F_7/2,⁴I_15/2→⁴I_13/2}和{⁴G_9/2→⁴I_13/2, ⁴I_15/2→²H_11/2}是导致Er_1.0P₅O₁₄非晶玻璃具有强的三光子和四光子量子剪裁红外荧光的原因.研究结果对改善太阳能电池效率有一定意义.     

A-15型超导化合物转变温度与晶格常数关系的理论解释

本文根据文献[1]的理论,结合对势模型关于钒原子电子云的形变与内层电子从d_‖到d_⊥带转移量ν＇的关系,导出A-15型V₃B系化合物的超导临界温度了T_c与晶格常数α的关系,理论曲线与实验点的分布大体相符。     

测定超导体临界特性曲线的新方法

本文描述了测定超导体临界特性曲线的持续电流方法。和文献上通常采用的四引线方法相比较,本方法具有下列优点:(1)I_c(H)曲线的物理意义明确;(2)避免了向液氦杜瓦瓶内输入大电流时技术上的困难;(3)没有烧坏样品的危险。用本方法测量了冷加工铌线的I_c(H)曲线,结果证明了以前用四引线方法所得I_c(H)特性曲线中峯的存在。     

Hot-carrier degradation for 90nm gate length LDD-NMOSFET with ultra-thin gate oxide under low gate voltage stress

The hot-carrier degradation for 90~nm gate length lightly-doped drain (LDD) NMOSFET with ultra-thin (1.4~nm) gate oxide under the low gate voltage (LGV) (at V_g=V_th, where V_th is the threshold voltage) stress has been investigated. It is found that the drain current decreases and the threshold voltage increases after the LGV (V_g=V_th stress. The results are opposite to the degradation phenomena of conventional NMOSFET for the case of this stress. By analysing the gate-induced drain leakage (GIDL) current before and after stresses, it is confirmed that under the LGV stress in ultra-short gate LDD-NMOSFET with ultra-thin gate oxide, the hot holes are trapped at interface in the LDD region and cannot shorten the channel to mask the influence of interface states as those in conventional NMOSFET do, which leads to the different degradation phenomena from those of the conventional NMOS devices. This paper also discusses the degradation in the 90~nm gate length LDD-NMOSFET with 1.4~nm gate oxide under the LGV stress at V_g=V_th with various drain biases. Experimental results show that the degradation slopes (n) range from 0.21 to 0.41. The value of n is less than that of conventional MOSFET (0.5-0.6) and also that of the long gate length LDD MOSFET (\sim0.8).     

A GaAs MISFET with Ge3N4 gate dielectric

GaAs MIS field effect transistors with a Ge₃N₄ dielectric gate have been investigated. No hysteresis loop and drain current drift has been observed in theI _D -V _Dcharacteristics. However, performance of the devices have been found to be limited by the contact resistance. FromI _DS ^1/2 -V _G plot, the threshold voltage and effective channel mobility of the transistor have been obtained as -4.5V and 2800cm²v^–1s^–1, respectively. A maximum dc transconductance of 68 mS/mm of gate width has been achieved.     

A study on the performance of metal-oxide-semiconductor-field-effect-transistors with asymmetric junction doping structure

Diode currents of MOSFET were studied and characterized in detail for the ion implanted pn junction of short channel MOSFETs with shallow drain junction doping structure. The diode current in MOSFET junctions was analyzed on the point of view of the gate-induced-drain leakage (GIDL) current. We could found the GIDL current is generated by the band-to-band tunneling (BTBT) of electrons through the reverse biased channel-to-drain junction and had good agreement with BTBT equation. The effect of the lateral electric field on the GIDL current according to the body bias voltage is characterized and discussed. We measured the electrical doping profiling of MOSFETs with a short gate length, ultra thin oxide thickness and asymmetric doped drain structure and checked the profile had good agreement with simulation result. An accurate effective mobility of an asymmetric source–drain junction transistor was successfully extracted by using the split C–V technique.     

低栅极电压控制下带有phenyltrimethoxysilane单分子自组装层的有机薄膜晶体管场效应特性研究

制作了底栅极顶接触有机薄膜晶体管器件,60 nm的pentacene被用作有源层,120 nm热生长的SiO₂作为栅极绝缘层.通过采用不同自组装修饰材料对器件的有源层与栅极绝缘层之间的界面进行修饰,如octadecyltrichlorosilane （OTS）,phenyltrimethoxysilane （PhTMS）,来比较界面修饰层对器件性能的影响.同时对带有PhTMS修饰层的OTFTs器件低栅极电压调制下的场效应行为及其载流子的传输机理进行研究.结果得到,当|V 关键词： 有机薄膜晶体管 自组装单分子层 场效应迁移率 低栅极调制电压     

XOR gate response in a mesoscopic ring with embedded quantum dots

We address XOR gate response in a mesoscopic ring threaded by a magnetic flux . The ring, composed of identical quantum dots, is symmetrically attached to two semi-infinite one-dimensional metallic electrodes and two gate voltages, viz, V_a and V_b, are applied, respectively, in each arm of the ring which are treated as the two inputs of the XOR gate. The calculations are based on the tight-binding model and the Green’s function method, which numerically compute the conductance–energy and current–voltage characteristics as functions of the ring-electrodes coupling strengths, magnetic flux and gate voltages. Quite interestingly it is observed that, for =₀/2 (₀=ch/e, the elementary flux-quantum) a high output current (1) (in the logical sense) appears if one, and only one, of the inputs to the gate is high (1), while if both inputs are low (0) or both are high (1), a low output current (0) appears. It clearly demonstrates the XOR behavior and this aspect may be utilized in designing the electronic logic gate.     

高场应力及栅应力下AlGaN/GaN HEMT器件退化研究

采用不同的高场应力和栅应力对AlGaN/GaN HEMT器件进行直流应力测试,实验发现：应力后器件主要参数如饱和漏电流,跨导峰值和阈值电压等均发生了明显退化,而且这些退化还是可以完全恢复的;高场应力下,器件特性的退化随高场应力偏置电压的增加和应力时间的累积而增大;对于不同的栅应力,相对来说,脉冲栅应力和开态栅应力下器件特性的退化比关态栅应力下的退化大.对不同应力前后器件饱和漏电流,跨导峰值和阈值电压的分析表明,AlGaN势垒层陷阱俘获沟道热电子以及栅极电子在栅漏间电场的作用下填充虚栅中的表面态是这些不同应 关键词： AlGaN/GaN HEMT器件 表面态(虚栅) 势垒层陷阱 应力     

A low specific on-resistance SOI MOSFET with dual gates and recessed drain

A low specific on-resistance (R_on,sp) integrable silicon-on-insulator (SOI) metal-oxide semiconductor field-effect transistor (MOSFET) is proposed and investigated by simulation. The MOSFET features a recessed drain as well as dual gates which consist of a planar gate and a trench gate extended to the buried oxide layer (BOX) (DGRD MOSFET). First, the dual gates form dual conduction channels, and the extended trench gate also acts as a field plate to improve the electric field distribution. Second, the combination of the trench gate and the recessed drain widens the vertical conduction area and shortens the current path. Third, the P-type top layer not only enhances the drift doping concentration but also modulates the surface electric field distributions. All of these sharply reduce R_on,sp and maintain a high breakdown voltage (BV). The BV of 233 V and R_on,sp of 4.151 mΩ·cm² (V_GS=15 V) are obtained for the DGRD MOSFET with 15-μm half-cell pitch. Compared with the trench gate SOI MOSFET and the conventional MOSFET, R_on,sp of the DGRD MOSFET decreases by 36% and 33% with the same BV, respectively. The trench gate extended to the BOX synchronously acts as a dielectric isolation trench, simplifying the fabrication processes.     

Nb/BiSCCO point conctact junctions

Summary Preparation procedure and sample characterization of 112 BiSCCO pellets exhibiting high-T _c superconductivity are discussed. TypicalI–V and dV/dI curves of Nb/BiSCCO point conctact junctions at various temperatures are presented.     

The electrical characteristics of a 4H-silicon carbide metal-insulator-semiconductor structure with Al2O3 as the gate dielectric

A 4H-silicon carbide metal-insulator-semiconductor structure with ultra-thin Al₂O₃ as the gate dielectric, deposited by atomic layer deposition on the epitaxial layer of a 4H-SiC (0001) 8⁰N-/N+ substrate, has been fabricated. The experimental results indicate that the prepared ultra-thin Al₂O₃ gate dielectric exhibits good physical and electrical characteristics, including a high breakdown electrical field of 25 MV/cm, excellent interface properties (1×10¹⁴ cm^-2) and low gate-leakage current (I_G = 1 × 10^-3 A/cm^-2@E_ox = 8 MV/cm). Analysis of the current conduction mechanism on the deposited Al₂O₃ gate dielectric was also systematically performed. The confirmed conduction mechanisms consisted of Fowler-Nordheim (FN) tunneling, the Frenkel-Poole mechanism, direct tunneling and Schottky emission, and the dominant current conduction mechanism depends on the applied electrical field. When the gate leakage current mechanism is dominated by FN tunneling, the barrier height of SiC/Al₂O₃ is 1.4 eV, which can meet the requirements of silicon carbide metal-insulator-semiconductor transistor devices.