一步掩膜法制备超低压ITO沟道纸上薄膜晶体管

基于一步掩模法工艺制备了一种新型的纸上双电荷层超低压薄膜晶体管. 在室温射频磁控溅射过程中, 仅仅利用一块镍掩模板, 就可同时沉积出氧化铟锡(ITO)源漏电极和ITO沟道. 在此基础上, 以等离子体增强化学气相沉积法(PECVD)合成的具有双电荷层效应的微孔SiO₂为栅介质, 成功制备出以纸为衬底的超低压氧化物薄膜晶体管. 这种晶体管显示出极好的性能: 超低的工作电压1.5 V, 场效应迁移率为20.1 cm²/Vs, 亚阈值斜率为188 mV/decade, 开关电流比为5× 10⁵. 这种基于全室温一步掩模法工艺制备的纸上氧化物薄膜晶体管具有工作电压低, 工艺简单, 成本低廉等优点, 非常有望应用于未来便携式低功耗电子产品的制造中.     

In2O3 透明薄膜晶体管的制备及其电学性能的研究

采用磁控溅射方法在玻璃衬底上生长了In₂O₃晶体薄膜.该薄膜具有(111)晶面择优取向,晶粒尺寸达到33 nm.利用光刻工艺制作了以In₂O₃晶体薄膜为沟道层的底栅式薄膜晶体管.In₂O₃薄膜晶体管具有良好的栅压调制特性,场效应迁移率达到6.3 cm²/(V·s),开关电流比为3×10³,阈值电压为-0.9 V.结果表明,In相似文献   

室温下溅射法制备高迁移率氧化锌薄膜晶体管

为降低氧化锌薄膜晶体管(ZnO TFT)的工作电压,提高迁移率,采用磁控溅射法在氧化铟锡(ITO)导电玻璃基底上室温下依次沉积NbLaO栅介质层和ZnO半导体有源层,制备出ZnO TFT,对器件的电特性进行了表征。该ZnO TFT呈现出优异的器件性能:当栅电压为5 V、漏源电压为10 V时,器件的饱和漏电流高达2.2 m A;有效场效应饱和迁移率高达107 cm~2/(V·s),是目前所报道的室温下溅射法制备ZnO TFT的最高值,亚阈值摆幅为0.28 V/decade,开关电流比大于107。利用原子力显微镜(AFM)对NbLaO和ZnO薄膜的表面形貌进行了分析,分析了器件的低频噪声特性,对器件呈现高迁移率、低亚阈值摆幅以及迟滞现象的机理进行了讨论。     

双电层氧化锌薄膜晶体管偏压应力稳定性

以环保可降解的天然生物材料制备功能器件越来越受到关注,利用天然鸡蛋清作为栅介质层,采用射频磁控溅射法在其上沉积ZnO薄膜有源层,制备低压双电层氧化锌基薄膜晶体管（ZnO-TFT）并对其电学特性进行了表征,研究了器件在栅偏压和漏偏压应力下电性能的稳定性及其内在的物理机制。该ZnO-TFT器件呈现出良好的电特性,载流子饱和迁移率为5.99 cm²/（V·s）,阈值电压为2.18 V,亚阈值摆幅为0.57 V/dec,开关电流比为1.2×10⁵,工作电压低至3 V。研究表明,在偏压应力作用下,该ZnO-TFT器件电性能存在一定的不稳定性,我们认为栅偏压应力引起的电性能变化可能来源于栅介质附近及界面处的正电荷聚集、充放电效应和新陷阱态的复合效应;漏偏压应力引起的电性能变化可能来源于焦耳热引起的氧空位及沟道中的电子陷阱。     

基于P掺杂SiO2为栅介质的超低压侧栅薄膜晶体管

在室温下利用等离子体增强化学气相沉积法(PECVD)制备的颗粒膜P掺杂SiO₂为栅介质, 使用磁控溅射方法利用一步掩模法制备出一种新型结构的侧栅薄膜晶体管. 由于侧栅薄膜晶体管具有独特的结构, 在射频磁控溅射过程中, 仅仅利用一块镍掩模板, 无需复杂的光刻步骤, 就可同时沉积出氧化铟锡(ITO)源、漏、栅电极和沟道, 因此, 这种方法极大地简化了制备流程, 降低了工艺成本. 实验结果表明, 在P掺杂SiO₂栅介质层与沟道层界面处形成了超大的双电层电容(8 μF/cm²), 这使得这类晶体管具有超低的工作电压1 V, 小的亚阈值摆幅82 mV/dec、高的迁移率18.35 cm²/V·s和大的开关电流比1.1×10⁶. 因此, 这种P掺杂SiO₂双电层超低压薄膜晶体管将有望应用于低能耗便携式电子产品以及新型传感器领域. 关键词： 2')" href="#">P掺杂SiO₂ 侧栅薄膜晶体管 双电层(EDL) 超低压     

氧对IZO低压无结薄膜晶体管稳定性的影响

本文在室温下制备了无结结构的低压氧化铟锌薄膜晶体管, 并研究了氧分压对其稳定性的影响. 氧化铟锌无结薄膜晶体管具有迁移率高、结构新颖等优点, 然而氧化物沟道层易受氧、水分子等影响, 造成稳定性下降. 在室温下, 本文通过改变高纯氧流量制备氧化铟锌透明导电薄膜作为沟道层、源漏电极, 分析了氧压对于氧化物无结薄膜晶体管稳定性的影响. 为使晶体管在低电压(<2 V)下工作, 达到低压驱动效果, 本文采用具有双电层效应和栅电容大的二氧化硅纳米颗粒膜作为栅介质; 通过电学性能测试, 制备的晶体管工作电压仅为1 V、 开关电流比大于10⁶、亚阈值斜率小于100 mV/decade以及场效 应迁移率大于20 cm²/V·s. 实验研究表明, 通氧制备的氧化铟锌薄膜的电阻率会上升, 导致晶体管的阈值电压向正向漂移, 最终使晶体管的工作模式由耗尽型转变为增强型. 关键词： 薄膜晶体管 无结 氧化铟锌 氧分子     

基于蛋清栅介质的超低压双电层薄膜晶体管

新一代环保、生物兼容性电子功能器件受到了广泛关注.本文采用具有高质子导电特性的天然鸡蛋清作为耦合电解质膜制备双电层薄膜晶体管,该薄膜晶体管以氧化铟锡导电玻璃为衬底和底电极,以旋涂法制备的鸡蛋清为栅介质,以磁控溅射沉积的氧化铟锌为沟道和源漏电极.实验结果表明,这种基于鸡蛋清的栅介质具有良好的绝缘性,并能在其与沟道界面处形成巨大的双电层电容,从而使得该类晶体管具有超低工作电压（1.5 V）、低亚阈值（164 mV/dec）、大电流开关比（2.4×10⁶）和较高的饱和区场效应迁移率（38.01 cm²/（V· s））.这种以天然鸡蛋清为栅介质的超低压双电层TFTs有望应用于新型生物电子器件及低能耗便携式电子产品.     

栅漏间表面外延层对4H-SiC功率MESFET击穿 特性的改善机理与结构优化

本文提出了一种带栅漏间表面p型外延层的新型MESFET结构并整合了能精确描述4H-SiC MESFET工作机理的数值模型,模型综合考虑了高场载流子饱和、雪崩碰撞离化以及电场调制等效应. 利用所建模型分析了表面外延层对器件沟道表面电场分布的改善作用,并采用突变结近似法对p型外延层参数与器件输出电流(I_ds)和击穿电压(V_B)的关系进行了研究.结果表明,通过在常规MESFET漏端处引入新的电场峰来降低栅极边缘的强电场峰并在栅漏之间的沟道表面引入p-n结内建电场进一步降低电场峰值,改善了表面电场沿电流方向的分布.通过与常规结构以及场板结构SiC MESFET的特性对比表明,本文提出的结构可以明显改善SiC MESFET的功率特性.此外,针对文中给定的器件结构,获得了优化的设计方案,选择p型外延层厚度为0.12 μupm,掺杂浓度为5× 10¹⁵ cm^-3,可使器件的V_B提高33%而保持I_ds基本不变.     

非晶铟镓锌氧薄膜晶体管钼/铜源漏电极的研究

针对非晶铟镓锌氧薄膜晶体管（a-IGZO TFT）的钼/铜源漏电极开展研究。实验证明,单层Mo源漏电极与栅绝缘层之间的粘附性好、表面粗糙度较小、电阻率较大,而单层Cu源漏电极与栅绝缘层之间的结合性差且Cu原子扩散问题严重、表面粗糙度较大、电阻率较小。为了实现优势互补,我们设计了双层Mo（20 nm）/Cu（80 nm）源漏电极,并采用优化工艺制备了包含该电极结构的a-IGZO TFT。器件具有良好的电学特性,场效应迁移率为 8.33 cm²·V^-1·s^-1, 阈值电压为6.0 V,亚阈值摆幅为2.0 V/dec,开关比为 1.3×10⁷,证明了双层Mo/Cu源漏电极的可行性和实用性。     

沟道层厚度对室温制备的In2O3薄膜晶体管器件性能的影响

在室温下采用直流磁控溅射以SiO₂/Si为衬底制备了不同沟道层厚度的底栅式In₂O₃薄膜晶体管,讨论了沟道层厚度对底栅In₂O₃薄膜晶体管的电学性能的影响。实验结果表明:器件的特性与沟道层厚度有关,最优沟道层厚度的In₂O₃薄膜晶体管为增强型,其阈值电压为2.5 V,开关电流比约为10⁶,场效应迁移率为6.2 cm²·V^-1·s^-1。     

Low-voltage-drive and high output current ZnO thin-film transistors with sputtering SiO2 as gate insulator

Low-voltage-drive ZnO thin-film transistors (TFTs) with room-temperature radio frequency magnetron sputtering SiO₂ as the gate insulator were fabricated successfully on the glass substrate. The ZnO-TFT operates in the enhancement mode with a threshold voltage of 4.2 V, a field effect mobility of 11.2 cm²/V s, an on/off ratio of 3.1 × 10⁶ and a subthreshold swing of 0.61 V/dec. The drain current can reach to 1 mA while the gate voltage is only of 12 V and drain voltage of 8 V. The C–V characteristics of a MOS capacitor with the structure of ITO/SiO₂/ZnO/Al was investigated. The carrier concentration N_D in the ZnO active layer was determined, the calculated N_D is 1.81 × 10¹⁶ cm⁻³, which is the typical value of undoped ZnO film used as the channel layer for ZnO-TFT devices. The experiment results show that SiO₂ film is a promising insulator for the low voltage and high drive capability oxide TFTs.     

Amorphous IZO TTFTs with saturation mobilities exceeding 100 cm2/Vs

In this paper we demonstrate the use of amorphous binary In₂O₃–ZnO oxides simultaneously as active channel layer and as source/drain regions in transparent thin film transistor (TTFT), processed at room temperature by rf sputtering. The TTFTs operate in the enhancement mode and their performances are thickness dependent. The best TTFTs exhibit saturation mobilities higher than 10² cm²/Vs, threshold voltages lower than 6 V, gate voltage swing of 0.8 V/dec and an on/off current ratio of 10⁷. This mobility is at least two orders of magnitude higher than that of conventional amorphous silicon TFTs and comparable to or even better than other polycrystalline semiconductors. (© 2007 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)     

Low-voltage antimony-doped SnO2 nanowire transparent transistors gated by microporous SiO2-based proton conductors

A battery drivable low-voltage transparent lightly antimony（Sb）-doped SnO2 nanowire electric-double-layer （EDL） field-effect transistor （FET） is fabricated on an ITO glass substrate at room temperature. An ultralow operation voltage of 1 V is obtained on account of an untralarge specific gate capacitance （- 2.14 μF/cm2） directly bound up with mobile ions-induced EDL （sandwiched between the top and bottom electrodes） effect. The transparent FET shows excellent electric characteristics with a field-effect mobility of 54.43 cm2/V. s, current on/off ration of 2 × 104, and subthreshold gate voltage swing （S = dVgs/d（logIds）） of 140 mV/decade. The threshold voltage Yth （0.1 V） is estimated which indicates that the SnO2 namowire transistor operates in an n-type enhanced mode. Such a low-voltage transparent nanowire transistor gated by a microporous SiO2-based solid electrolyte is very promising for battery-powered portable nanoscale sensors.     

High‐performance In–Zn–O thin‐film transistors with a soluble processed ZrO2 gate insulator

Spin‐coated zirconium oxide films were used as a gate dielectric for low‐voltage, high performance indium zinc oxide (IZO) thin‐film transistors (TFTs). The ZrO₂ films annealed at 400 °C showed a low gate leakage current density of 2 × 10^–8 A/cm² at an electric field of 2 MV/cm. This was attributed to the low impurity content and high crystalline quality. Therefore, the IZO TFTs with a soluble ZrO₂ gate insulator exhibited a high field effect mobility of 23.4 cm²/V s, excellent subthreshold gate swing of 70 mV/decade and a reasonable I_on/off ratio of ～10⁶. These TFTs operated at low voltages (～3.0 V) and showed high drain current drive capability, enabling oxide TFTs with a soluble processed high‐k dielectric for use in backplane electronics for low‐power mobile display applications. (© 2013 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)     

High performance Zn–Sn–O thin film transistors with Cu source/drain electrode

Zn–Sn–O (ZTO) thin film transistors (TFTs) were fabricated with a Cu source/drain electrode. Although a reasonably high mobility (μ_FE) of 13.2 cm²/Vs was obtained for the ZTO TFTs, the subthreshold gate swing (SS) and threshold voltage (V_th) of 1.1 V/decade and 9.1 V, respectively, were inferior. However, ZTO TFTs with Ta film inserted as a diffusion barrier, exhibited improved SS and V_th values of 0.48 V/decade and 3.0 V, respectively as well as a high μ_FE value of 18.7 cm²/Vs. The improvement in the Ta‐inserted device was attributed to the suppression of Cu lateral diffusion into the ZTO channel region. (© 2013 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)     

High-performance amorphous indium gallium zinc oxide thin-film transistors with sol-gel processed gate dielectric and channel layer fabricated using microwave irradiation

In this study, we fabricated high-performance a-IGZO TFTs by forming Al₂O₃ and a-IGZO thin films for gate insulator and active channel layer, respectively, using a sol-gel process. MWI for low thermal budget process was used to condensate Al₂O₃ and a-IGZO films, which was compared with the CTA. It is found that the MWI is superior process to the conventional method in terms of precursor and solvent decomposition and has proven to be more effective for eliminating residual organic contaminants. In addition, the MWI-treated Al₂O₃ and IGZO films have smoother surfaces, higher visible light transmittance, lower carbon contamination and impurities than the CTA-treated films. We have demonstrated that a-IGZO TFTs with sol-gel solution-processed Al₂O₃ gate insulator and a-IGZO channel layer can achieve a field effect mobility of 69.2 cm²/V·s, a subthreshold swing of 86.2 mV/decade and a large on/off current ratio of 1.48 × 10⁸, by the MWI process even at temperatures below 200 °C. In addition, the MWI-treated a-IGZO TFTs have excellent resistance to electron trapping and good stability to positive and negative gate-bias stress. Therefore, the sol-gel processed a-IGZO TFTs with Al₂O₃ gate oxide and the MWI treatment with a low thermal budget are promising for emerging transparent flat panel displays applications.     

Pulsed laser deposition of ZnO grown on glass substrates for realizing high-performance thin-film transistors

We report characterization of ZnO thin-film transistors (TFTs) on glass substrates fabricated by pulsed laser deposition (PLD). ZnO films were characterized by X-ray diffraction (XRD), atomic force microscopy and Hall effect measurements. The XRD results showed high c-axis-oriented ZnO(0002) diffraction corresponding to the wurtzite phase. Moreover, the crystallization and the electrical properties of ZnO thin films grown at room temperature are controllable by PLD growth conditions such as oxygen gas pressure. The ZnO films are very smooth, with a root-mean-square roughness of 1 nm. From the Hall effect measurements, we have succeeded in fabricating ZnO films on glass substrates with an electron mobility of 21.7 cm²/V s. By using the ZnO thin film grown by two-step PLD and a HfO₂ high-k gate insulator, a transconductance of 24.1 mS/mm, a drain current on/off ratio of 4.4×10⁶ and a subthreshold gate swing of 0.26 V/decade were obtained for the ZnO TFT.