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In this paper, 1.2 kV, 3.3 kV, and 5.0 kV class 4H–SiC power Schottky barrier diodes(SBDs)are fabricated with three N-type drift layer thickness values of 10 μm, 30 μm, and 50 μm, respectively. The avalanche breakdown capabilities,static and transient characteristics of the fabricated devices are measured in detail and compared with the theoretical predictions. It is found that the experimental results match well with the theoretical calculation results and are very close to the 4H–SiC theoretical limit line. The best achieved breakdown voltages(BVs) of the diodes on the 10 μm, 30 μm, and 50 μm epilayers are 1400 V, 3320 V, and 5200 V, respectively. Differential specific-on resistances(R_(on-sp)) are 2.1 m?·cm~2,7.34m?·cm~2, and 30.3 m?·cm~2, respectively.  相似文献   
2.
In this paper, the normally-off N-channel lateral 4H–Si C metal–oxide–semiconductor field-effect transistors(MOSFFETs) have been fabricated and characterized. A sandwich-(nitridation–oxidation–nitridation) type process was used to grow the gate dielectric film to obtain high channel mobility. The interface properties of 4H–Si C/SiO_2 were examined by the measurement of HF I–V, G–V, and C–V over a range of frequencies. The ideal C–V curve with little hysteresis and the frequency dispersion were observed. As a result, the interface state density near the conduction band edge of 4H–Si C was reduced to 2 × 10~(11) e V~(-1)·cm~(-2), the breakdown field of the grown oxides was about 9.8 MV/cm, the median peak fieldeffect mobility is about 32.5 cm~2·V~(-1)·s~(-1), and the maximum peak field-effect mobility of 38 cm~2·V~(-1)·s~(-1) was achieved in fabricated lateral 4H–Si C MOSFFETs.  相似文献   
3.
Near-interface oxide traps(NIOTs)in 4H–Si C metal–oxide–semiconductor(MOS)structures fabricated with and without annealing in NO are systematically investigated in this paper.The properties of NIOTs in Si C MOS structures prepared with and without annealing in NO are studied and compared in detail.Two main categories of the NIOTs,the"slow"and"fast"NIOTs,are revealed and extracted.The densities of the"fast"NIOTs are determined to be 0.76×10~(11)cm~(-2)and0.47×10~(11)cm~(-2)for the N_2 post oxidation annealing(POA)sample and NO POA sample,respectively.The densities of"slow"NIOTs are 0.79×10~(11)cm~(-2)and 9.44×10~(11)cm~(-2)for the NO POA sample and N_2POA sample,respectively.It is found that the NO POA process only can significantly reduce"slow"NIOTs.However,it has a little effect on"fast"NIOTs.The negative and positive constant voltage stresses(CVS)reveal that electrons captured by those"slow"NIOTs and bulk oxide traps(BOTs)are hardly emitted by the constant voltage stress.  相似文献   
4.
This paper presents the development of lateral depletion-mode n-channel 4 H-SiC junction field-effect transistors(LJFETs)using double-mesa process toward high-temperature integrated circuit(IC)applications.At room temperature,the fabricated LJFETs show a drain-to-source saturation current of 23.03μA/μm,which corresponds to a current density of 7678 A/cm2.The gate-to-source parasitic resistance of 17.56 kΩ·μm is reduced to contribute only 13.49%of the on-resistance of 130.15 kΩ·μm,which helps to improve the transconductance up to 8.61μS/μm.High temperature characteristics of LJFETs were performed from room temperature to 400℃.At temperatures up to 400℃in air,it is observed that the fabricated LJFETs still show normally-on operating characteristics.The drain-to-source saturation current,transconductance and intrinsic gain at 400℃are 7.47μA/μm,2.35μS/μm and 41.35,respectively.These results show significant improvement over state-of-the-art and make them attractive for high-temperature IC applications.  相似文献   
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