区组长为奇素数的自反MD设计 (英)

本文利用差方法对自反MD设计SCMD$(4mp, p,1)$的存在性给出了构造性证明, 这里$p$为奇素数, $m$为正整数.     

区组长为奇素数的自反MD设计

本文利用差方法对自反MD设计SCMD(4mp,p,1)的存在性给出了构造性证明,这里p为奇素数,m为正整数．     

Near-interface oxide traps in 4H–SiC MOS structures fabricated with and without annealing in NO

Near-interface oxide traps(NIOTs)in 4H–Si C metal–oxide–semiconductor(MOS)structures fabricated with and without annealing in NO are systematically investigated in this paper.The properties of NIOTs in Si C MOS structures prepared with and without annealing in NO are studied and compared in detail.Two main categories of the NIOTs,the"slow"and"fast"NIOTs,are revealed and extracted.The densities of the"fast"NIOTs are determined to be 0.76×10~(11)cm~(-2)and0.47×10~(11)cm~(-2)for the N_2 post oxidation annealing(POA)sample and NO POA sample,respectively.The densities of"slow"NIOTs are 0.79×10~(11)cm~(-2)and 9.44×10~(11)cm~(-2)for the NO POA sample and N_2POA sample,respectively.It is found that the NO POA process only can significantly reduce"slow"NIOTs.However,it has a little effect on"fast"NIOTs.The negative and positive constant voltage stresses(CVS)reveal that electrons captured by those"slow"NIOTs and bulk oxide traps(BOTs)are hardly emitted by the constant voltage stress.