源、漏到栅距离对次亚微米ggNMOS ESD保护电路鲁棒性的影响

基于对静电放电(electrostatic discharge,ESD)应力下高电压、大电流特性的研究,本文通过优化晶格自加热漂移-扩散模型和热力学模型,并应用优化模型建立了全新的0.6 μm CSMC 6S06DPDM-CT02 CMOS工艺下栅接地NMOS (gate grounded NMOS,ggNMOS)ESD保护电路3D模型,对所建模型中漏接触孔到栅距离(drain contact to gate spacing,DCGS)与源接触孔到栅距离(source contact to gate sp 关键词： 栅接地NMOS 静电放电 漏接触孔到栅的距离 源接触孔到栅的距离     

Statistical Elmore delay of RC interconnect tree

As feature size keeps scaling down,process variations can dramatically reduce the accuracy in the estimation of interconnect performance.This paper proposes a statistical Elmore delay model for RC interconnect tree in the presence of process variations.The suggested method translates the process variations into parasitic parameter extraction and statistical Elmore delay evaluation.Analytical expressions of mean and standard deviation of interconnect delay can be obtained in a given fluctuation range of interconnect geometric parameters.Experimental results demonstrate that the approach matches well with Monte Carlo simulations.The errors of proposed mean and standard deviation are less than 1% and 7%,respectively.Simulations prove that our model is efficient and accurate.     

β-SiC薄膜在SF6和SF6+O2中的等离子体刻蚀研究

以SF₆和SF₆+O₂为刻蚀气体,采用等离子体刻蚀工艺成功地对化学气相淀积工艺制备的β-SiC单晶薄膜进行了有效的刻蚀去除.实验指出当气体混合比约为40%时,刻蚀速率达到最大值.俄歇能谱分析表明,在SF₆和SF₆+O₂气体中被刻蚀后的样品没有形成富C表面的SiC层.研究结果为各种SiC器件的研制奠定了必要的实验基础. 关键词：     

Pulsed microwave damage trend of bipolar transistor as a function of pulse parameters

In the present paper we conduct a theoretical study of the thermal accumulation effect of a typical bipolar transistor caused by high power pulsed microwave (HPM), and investigate the thermal accumulation effect as a function of pulse repetition frequency (PRF) and duty cycle. A study of the damage mechanism of the device is carried out from the variation analysis of the distribution of the electric field and the current density. The result shows that the accumulation temperature increases with PRF increasing and the threshold for the transistor is about 2 kHz. The response of the peak temperature induced by the injected single pulses indicates that the falling time is much longer than the rising time. Adopting the fitting method, the relationship between the peak temperature and the time during the rising edge and that between the peak temperature and the time during the falling edge are obtained. Moreover, the accumulation temperature decreases with duty cycle increasing for a certain mean power.     

Damage effect and mechanism of the GaAs pseudomorphic high electron mobility transistor induced by the electromagnetic pulse

The damage effect and mechanism of the electromagnetic pulse(EMP) on the GaAs pseudomorphic high electron mobility transistor(PHEMT) are investigated in this paper. By using the device simulation software, the distributions and variations of the electric field, the current density and the temperature are analyzed. The simulation results show that there are three physical effects, i.e., the forward-biased effect of the gate Schottky junction, the avalanche breakdown, and the thermal breakdown of the barrier layer, which influence the device current in the damage process. It is found that the damage position of the device changes with the amplitude of the step voltage pulse. The damage appears under the gate near the drain when the amplitude of the pulse is low, and it also occurs under the gate near the source when the amplitude is sufficiently high, which is consistent with the experimental results.     

New 4H silicon carbide metal semiconductor field-effect transistor with a buffer layer between the gate and the channel layer

A new 4H silicon carbide metal semiconductor field-effect transistor (4H-SiC MESFET) structure with a buffer layer between the gate and the channel layer is proposed in this paper for high power microwave applications.The physics-based analytical models for calculating the performance of the proposed device are obtained by solving one-and two-dimensional Poisson’s equations.In the models,we take into account not only two regions under the gate but also a third high field region between the gate and the drain which is usually omitted.The direct-current and the alternatingcurrent performances for the proposed 4H-SiC MESFET with a buffer layer of 0.2 μm are calculated.The calculated results are in good agreement with the experimental data.The current is larger than that of the conventional structure.The cutoff frequency (fT) and the maximum oscillation frequency (f max) are 20.4 GHz and 101.6 GHz,respectively,which are higher than 7.8 GHz and 45.3 GHz of the conventional structure.Therefore,the proposed 4H-SiC MESFET structure has better power and microwave performances than the conventional structure.     

红外保护膜性能评估和分析

讨论红外保护膜的作用，分析和介绍保护膜的机械强度以及保护膜的外应力和内应力产生的破坏和影响，并提出了应对措施，探讨保护膜在恶劣环境下的光学性能，指出优化控制膜厚的重要性。     

GaN高电子迁移率晶体管强电磁脉冲损伤效应与机理

提出了一种新型GaN异质结高电子迁移率晶体管在强电磁脉冲下的二维电热模型,模型引入材料固有的极化效应,高场下电子迁移率退化、载流子雪崩产生效应以及器件自热效应,分析了栅极注入强电磁脉冲情况下器件内部的瞬态响应,对其损伤机理和损伤阈值变化规律进行了研究.结果表明,器件内部温升速率呈现出"快速-缓慢-急剧"的趋势.当器件局部温度足够高时(2000 K),该位置热电子发射与温度升高形成正反馈,导致温度急剧升高直至烧毁.栅极靠近源端的柱面处是由于热积累最易发生熔融烧毁的部位,严重影响器件的特性和可靠性.随着脉宽的增加,损伤功率阈值迅速减小而损伤能量阈值逐渐增大.通过数据拟合得到脉宽τ与损伤功率阈值P和损伤能量阈值E的关系.     

Hardening measures for bipolar transistors against microwave-induced damage

In the present paper we study the influences of the bias voltage and the external components on the damage progress of a bipolar transistor induced by high-power microwaves. The mechanism is presented by analyzing the variation in the internal distribution of the temperature in the device. The findings show that the device becomes less vulnerable to damage with an increase in bias voltage. Both the series diode at the base and the relatively low series resistance at the emitter, Re, can obviously prolong the burnout time of the device. However, Re will aid damage to the device when the value is sufficiently high due to the fact that the highest hot spot shifts from the base-emitter junction to the base region. Moreover, the series resistance at the base Rb will weaken the capability of the device to withstand microwave damage.     

Modeling of the drain-induced barrier lowering effect and optimization for a dual-channel 4H silicon carbide metal semiconductor field effect transistor

A new analytical model to describe the drain-induced barrier lowering (DIBL) effect has been obtained by solving the two-dimensional (2D) Poisson's equation for the dual-channel 4H-SiC MESFET (DCFET). Using this analytical model, we calculate the threshold voltage shift and the sub-threshold slope factor of the DCFET, which characterize the DIBL effect. The results show that they are significantly dependent on the drain bias, gate length as well as the thickness and doping concentration of the two channel layers. Based on this analytical model, the structure parameters of the DCFET have been optimized in order to suppress the DIBL effect and improve the performance.