Positive gate-bias temperature instability of ZnO thin-film transistor

The positive gate-bias temperature instability of a radio frequency （RF） sputtered ZnO thin-film transistor （ZnO TFT） is investigated. Under positive gate-bias stress, the saturation drain current and OFF-state current decrease, and the threshold voltage shifts toward the positive direction. The stress amplitude and stress temperature are considered as important factors in threshold-voltage instability, and the time dependences of threshold voltage shift under various bias temperature stress conditions could be described by a stretched-exponential equation. Based on the analysis of hysteresis behaviors in current- voltage and capacitance-voltage characteristics before and after the gate-bias stress, it can be clarified that the threshold- voltage shift is predominantly attributed to the trapping of negative charge carriers in the defect states located at the gate- dielectric/channel interface.     

Calculations for shortening the bunch length in storage rings using a harmonic cavity

Using the Hefei Light Source phase Ⅱ project （HLS- Ⅱ） as an example, a theoretical analysis of shortening the bunch lengths using a higher harmonic cavity （HHC） is given. The threshold voltage of an active HHC and the threshold tuning angle of a passive HHC are first analysed. The optimum tuning angle for the constant detuning scenario and the optimum harmonic voltage for the constant voltage scenario are presented. The calculated results show that the reduced bunch length is about half that of the nominal bunch. The bunch lengths vary from 11 mm at 0.1 A to 7 mm at 0.4 A for the constant detuning scenario, while the bunch lengths are around 7 mm over the beam current range for the constant voltage scenario. In addition, the synchrotron frequency spread is increased. It indicates that HHC may be used to reduce the bunch length and increase the Landau damping of synchrotron oscillations in a storage ring.     

负电荷层对a-IGZO TFT阈值电压的影响

采用脉冲直流磁控溅射的方式沉积In-Ga-Zn-O (IGZO)膜层作为TFT的有源层.在TFT沟道处的有源层和绝缘层的界面上, 通过溅射法制作一定厚度的负电荷层对阈值电压(V_th)进行调制, 使得V_th由-3.8 V升高至-0.3 V, 器件由耗尽型向增强型转变.通过增加Al₂O₃作为负电荷层, 可有效地将V_th控制在0 V附近, 并且提高其器件稳定性, 得到较好的电学特性:电流开关比I_on/I_off>10⁹, 亚阈值摆幅SS为0.2 V/dec, 阈值电压V_th为-0.3 V, 迁移率μ为9.2 cm² /(V·s).     

Characteristics in AlN/AlGaN/GaN Multilayer-Structured High-Electron-Mobility Transistors

A new multilayer-structured AlN/AlCaN/CaN heterostructure high-electron-mobility transistor （HEMT） is demonstrated. The AIN/AlCaN/CaN HEMT exhibits the maximum drain current density of 800mA/mm and the maximum extrinsic transconductance of 170 mS/mm. Due to the increase of the distance between the gate and the two-dimensional electron-gas channel, the threshold voltage shifts slightly to the negative. The reduced drain current collapse and higher breakdown voltage are observed on this AIN/AlGaN/CaN HEMT. The current gain cut-off frequency and the maximum frequency of oscillation are 18.5 CHz and 29.0 GHz, respectively.     

基于数据线控制发光的A-IGZO薄膜晶体管集成AMOLED像素电路

本文提出了一种采用铟镓锌氧化物（IGZO）薄膜晶体管（TFT）的有源矩阵有机发光二极管（AMOLED）显示器的新型补偿结构。它利用数据线关闭电源和驱动晶体管之间的控制晶体管,以抑制编程期间的泄漏电流。在所提出的电路和传统电路之间进行电路性能的比较,表明所提出的像素电路可以有效地补偿驱动晶体管的阈值电压偏移和迁移率变化。当V_TH飘移2 V和μ增加30%时,I_OLED误差率可以分别降低至小于5%和9%。此外,由于使用同时驱动方法,因此所需的最小编程时间可以被详细推导出来。所提出的像素电路的编程能力和机制已经通过FPGA平台和离散的场效应器件所证实。尽管所提出的像素电路具有非常简单的驱动结构,但它能够提高补偿精度。