基于FPGA ARM的高速U盘记录仪的设计

为了满足对高速串行数据长时间实时显示存储的要求,提出了一种采用FPGA+ARM作为主控制器结合大容量Flash缓冲的设计方案;系统前端采用FPGA串并转换并控制Flash进行数据采集,后端采用ARM进行实时显示存储;该系统采集速率高,能够采集高达8.45 Mbps的输入数据,存储容量可扩;系统是针对两路输入速度高达460 800 bps的串行数据而设计的,经测试验证,数据存储可靠稳定,可广泛应用于飞行装置上。     

第十讲数字信号处理与数字信号处理器(DSP)

文章简要介绍了“数字信号处理”与“数字信号处理器（DSP）”的发展历史．在数字信号处理的应用中，实时实现是非常重要的，而DSP在实时处理中，扮演了一个重要的角色．文章中还介绍了DSP在实际应用中的一些关键技术，例如DSP的种类和选型，DSP的开发工具，实时软件的开发过程等．最后，还介绍了一些DSP的应用实例，如语音编码器，视频电话和视频会议系统，用于雷达和声纳的DSP并行处理系统     

图像处理的结构层次建模

图像处理是应用广泛的现代工程技术 ,但直到现在尚无完备的数学模型体系 .依结构层次观点对其数学模型化进行探索 ,给出了图像处理的结构层次模型 ,将图像处理与数学科学中的常见数学理论联系起来 .同时 ,对目前常见图像处理器进行数学模型描述 .     

Quantum Fourier Transform-Based Arithmetic Logic Unit on a Quantum Processor

This study proposes and construct a primitive quantum arithmetic logic unit (qALU) based on the quantum Fourier transform (QFT). The qALU is capable of performing arithmetic ADD (addition) and logic NAND gate operations. It designs a scalable quantum circuit and presents the circuits for driving ADD and NAND operations on two-input and four-input quantum channels, respectively. By comparing the required number of quantum gates for serial and parallel architectures in executing arithmetic addition, it evaluates the performance. It also execute the proposed quantum Fourier transform-based qALU design on real quantum processor hardware provided by IBM. The results demonstrate that the proposed circuit can perform arithmetic and logic operations with a high success rate. Furthermore, it discusses in detail the potential implementations of the qALU circuit in the field of computer science, highlighting the possibility of constructing a soft-core processor on a quantum processing unit.     

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The discriminatory processor sharing queues with multiple classes of customers (abbreviated as DPS queues) are an important but difficult research direction in queueing theory, and it has many important practical applications in the fields of, such as, computer networks, manufacturing systems, transportation networks, and so forth. Recently, researchers have carried out some key work for the DPS queues. They gave the generating function of the steady-state joint queue lengths, which leads to the first two moments of the steady-state joint queue lengths. However, using the generating function to provide explicit expressions for the steady-state joint queue lengths has been a difficult and challenging problem for many years. Based on this, this paper applies the maximum entropy principle in the information theory to providing an approximate expression with high precision, and this approximate expression can have the same first three moments as those of its exact expression. On the other hand, this paper gives efficiently numerical computation by means of this approximate expression, and analyzes how the key variables of this approximate expression depend on the original parameters of this queueing system in terms of some numerical experiments. Therefore, this approximate expression has important theoretical significance to promote practical applications of the DPS queues. At the same time, not only do the methodology and results given in this paper provide a new line in the study of DPS queues, but they also provide the theoretical basis and technical support for how to apply the information theory to the study of queueing systems, queueing networks and more generally, stochastic models.     

On single processor scheduling problems with learning dependent on the number of processed jobs

The importance of the role that learning plays in manufacturing, industry and computer systems is undeniable as well as the profit that can be increased if this phenomenon is taken into consideration for short- and long-term optimization. In this paper, we focus on scheduling jobs on a single processor, where its effectiveness can increase with the number of processed jobs, to minimize one of the following objectives: the maximum completion time with the release dates, the maximum lateness and the number of late jobs. It is proved that these well known polynomially solvable problems become at least NP-hard with the considered learning models. To solve them we provide some elimination procedures that are used to construct a branch and bound algorithm. Furthermore, we propose some fast heuristics for the problem of minimizing the number of late jobs with the general model of the learning effect.     

A scribing laser marking system using DSP controller

Laser marking is an important branch of laser processing technology, and has been widely used in many fields of industry. Digital signal processor (DSP) is an incredibly fast and powerful microprocessor that can deal with signals in real time. Not only it is portable but has the ability to integrate the processing signals of subsystems. In this research, it is emphasized that we designed a scribing laser marking system based on a DSP in galvanometric marking method. To control the rotating angle of the galvanometric scanning mirrors more accurately, we combine the D/A converter of the DSP with the human–machine interface successfully. The whole marking system is not only inexpensive, but also miniaturized.     

Research on Optical Transmitter and Receiver Module Used for High-Speed Interconnection between CPU and Memory

With the development of the multicore processor, the bandwidth and capacity of the memory, rather than the memory area, are the key factors in server performance. At present, however, the new architectures, such as fully buffered DIMM (FBDIMM), hybrid memory cube (HMC), and high bandwidth memory (HBM), cannot be commercially applied in the server. Therefore, a new architecture for the server is proposed. CPU and memory are separated onto different boards, and optical interconnection is used for the communication between them. Each optical module corresponds to each dual inline memory module (DIMM) with 64 channels. Compared to the previous technology, not only can the architecture realize high-capacity and wide-bandwidth memory, it also can reduce power consumption and cost, and be compatible with the existing dynamic random access memory (DRAM). In this article, the proposed module with system-in-package (SiP) integration is demonstrated. In the optical module, the silicon photonic chip is included, which is a promising technology to be applied in the next-generation data exchanging centers. And due to the bandwidth–distance performance of the optical interconnection, SerDes chips are introduced to convert the 64-bit data at 800 Mbps from/to 4-channel data at 12.8 Gbps after/before they are transmitted though optical fiber. All the devices are packaged on cheap organic substrates. To ensure the performance of the whole system, several optimization efforts have been performed on the two modules. High-speed interconnection traces have been designed and simulated with electromagnetic simulation software. Steady-state thermal characteristics of the transceiver module have been evaluated by ANSYS APLD based on finite-element methodology (FEM). Heat sinks are placed at the hotspot area to ensure the reliability of all working chips. Finally, this transceiver system based on silicon photonics is measured, and the eye diagrams of data and clock signals are verified.     

基于串行通信的高速DSP芯片 实验系统设计与实现

本文在总结国内外现有DSP仿真系统的基础上提出了一种借助单片机和串行通信实现数字信号处理程序实时运行和调试的新方法,并在此基础上介绍了在WINDOWS95平台下该DSP实验系统的设计过程。