150 kV全固态高压脉冲发生器设计

设计了一种基于全固态MOSFET半导体开关器件的Marx脉冲发生器。充电回路用快恢复二极管代替充电电阻,减小了充电部分功率损耗;将主电路和驱动电路集成在一起,采用自取电模式给驱动电路供电;由光纤传输驱动信号,抑制了放电回路对触发信号的干扰;采用顺/逆时针方向环形分布的紧凑型拓扑结构,不仅减小了回路电感,而且实现了脉冲发生器的小型化与模块化。所设计的Marx发生器充电部分仅需提供900 V低压,用180级单元串联,获得最高幅值为150 kV、脉宽1~5 s可调的高压快脉冲,前沿控制在500 ns以内。利用该脉冲发生器在50 k电阻和5 pF电容并联的等效负载上进行了一系列实验;比较分析了脉冲发生器工作过程中影响脉冲上升沿的几个主要因素,包括回路电感、MOSFET驱动电压及主回路分布电容等,并讨论了提升脉冲前沿的技术措施。     

Effects of Unintended Dopants on I-V Characteristics of the Double-Gate MOSFETs,a Simulation Study

In this paper, we study the effects of an unintended dopant in the channel on the current-voltage char-acteristics of a Double-Gate (DG) Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET). Non-Equilibrium Green's Function (NEGF) approach is used. A quantum transport model to calculate the drain current is presented and subthreshold swing and drain induced barrier lowering (DIBL) effect are studied.     

Simulation of CMOS logic inverter based on vertically stacked polycrystalline silicon nanosheet gate-all-around MOSFET and its electrical characteristics

The DC and inverter characteristics for the position of a single grain boundary (GB) in a nanosheet gate-all-around (GAA) MOSFET based on poly-crystalline silicon with three channels were analyzed. For the same channel layer, owing to the band banding by the drain voltage, the GB displays decreasing influence on the current as it moves towards the drain. The GB exhibits the highest on-state current of 6.89 × 10⁻⁴ A/μm when it is located at the drain. The DC characteristics determine the noise margin and delay time of the inverter. The higher the induced current, the lower the noise margin and delay time of the NMOS leading to improved characteristics of the inverter. The delay time when the GB existed in the drain, was considered to be the best in terms of DC performance as it was the lowest at 6.47 ps and showed 8.3% improvement in the switching characteristics.     

N/P沟道MOSFET1/f噪声的统一模型

对n／p两种沟道类型、不同沟道尺寸MOSFET的1／f噪声特性进行了实验和理论研究.实验结 果表明，虽然nMOSFET的1／f噪声幅值比pMOSFET大一个数量级，但是其噪声幅值均表现出和 有效栅压的平方成反比、和漏压的平方成正比、和沟道面积成反比的规律.基于该实验结果 ，认为MOSFET的1/f噪声产生机理为位于半导体_氧化物界面附近几个纳米范围内的氧化层陷 阱通过俘获和发射过程与沟道交换载流子，在引起载流子数涨落的同时也通过库仑散射导致 沟道载流子迁移率的涨落.在这两种涨落机理的基础上，引入了氧化层陷阱的分布特征及其 与沟道交换载流子的隧穿和热激活两种方式，建立了MOSFET l／f噪声的统一模型.实验结果 和本文模型符合良好. 关键词： 1/f噪声 MOSFET 氧化层陷阱 涨落     

Bipolar quantum corrections in resolving individual dopants in ‘atomistic’ device simulation

In ‘atomistic’ device simulation the resolving of discrete charges onto a fine-grained simulation mesh can lead to problems. The sharply resolved Coloumb potential can cause simulation artefacts to appear in classical simulation environments using Boltzmann or Fermi–Dirac statistics. Various methods have been proposed in an effort to reduce or eliminate such artefacts as the localisation of mobile carriers by sharply resolved Coulomb wells, however they have met with limited success. In this paper we present an alternative approach for handling discrete charges in drift diffusion ‘atomistic’ simulations by properly introducing the related quantum mechanical effects using the density gradient formalism for both electrons and holes. This eliminates the trapping of mobile charge in heavily doped regions of the device and the related artefacts in the simulated device characteristics.     

小尺寸MOSFET隧穿电流解析模型

基于表面势解析模型，通过将多子带等效为单子带，建立了耗尽/反型状态下小尺寸MOSFET直接隧穿栅电流解析模型.模拟结果与自洽解及实验结果均符合较好，表明此模型不仅可用于SiO₂、也可用于高介电常数(k)材料作为栅介质以及叠层栅介质结构MOSFET栅极漏电特性的模拟分析，计算时间较自洽解方法大大缩短，适用于MOS器件电路模拟. 关键词： 隧穿电流 MOSFET 量子机理 解析模型     

Improved 4H-SiC UMOSFET with super-junction shield region

This article investigates an improved 4H-SiC trench gate metal-oxide-semiconductor field-effect transistor (MOSFET) (UMOSFET) fitted with a super-junction (SJ) shielded region. The modified structure is composed of two n-type conductive pillars, three p-type conductive pillars, an oxide trench under the gate, and a light n-type current spreading layer (NCSL) under the p-body. The n-type conductive pillars and the light n-type current spreading layer provide two paths to and promote the diffusion of a transverse current in the epitaxial layer, thus improving the specific on-resistance ($R_{\rm on,sp}$). There are three p-type pillars in the modified structure, with the p-type pillars on both sides playing the same role. The p-type conductive pillars relieve the electric field ($E$-field) in the corner of the trench bottom. Two-dimensional simulation (silvaco TCAD) indicates that $R_{\rm on,sp }$ of the modified structure, and breakdown voltage ($V_{\rm BR}$) are improved by 22.2% and 21.1% respectively, while the maximum figure of merit (${\rm FOM}=V^{2}_{\rm BR}/R_{\rm on,sp}$) is improved by 79.0%. Furthermore, the improved structure achieves a light smaller low gate-to-drain charge ($Q_{\rm gd}$) and when compared with the conventional UMOSFET (conventional-UMOS), it displays great advantages for reducing the switching energy loss. These advantages are due to the fact that the p-type conductive pillars and n-type conductive pillars configured under the gate provide a substantial charge balance, which also enables the charge carriers to be extracted quickly. In the end, under the condition of the same total charge quantity, the simulation comparison of gate charge and OFF-state characteristics between Gauss-doped structure and uniform-doped structure shows that Gauss-doped structure increases the $V_{\rm BR}$ of the device without degradation of dynamic performance.     

Reduced self-heating by strained silicon substrate engineering

Substrate engineering innovations such as SOI and the use of Si/SiGe virtual substrates become necessary in order to maintain performance leverage of integrated circuits with continued scaling. The relevance of thermal effects in device design increases since the thermal conductivity of these new materials is poor. The electrical performance of devices fabricated on thin virtual substrates grown by two different techniques is presented. It is found that self-heating is reduced and that thermal resistance measurements agree with modelling predictions. The reduction in performance enhancement seen in many strained Si MOSFETs is found here to be largely due to self-heating effects, rather than parasitics or the loss of strain.     

Low on-resistance high-voltage lateral double-diffused metal oxide semiconductor with a buried improved super-junction layer

A novel low specific on-resistance （Ron,sp） lateral double-diffused metal oxide semiconductor （LDMOS） with a buried improved super-junction （BISJ） layer is proposed. A super-junction layer is buried in the drift region and the P pillar is split into two parts with different doping concentrations. Firstly, the buried super-junction layer causes the multiple-direction assisted depletion effect. The drift region doping concentration of the BISJ LDMOS is therefore much higher than that of the conventional LDMOS. Secondly, the buried super-junction layer provides a bulk low on-resistance path. Both of them reduce Ron,sp greatly. Thirdly, the electric field modulation effect of the new electric field peak introduced by the step doped P pillar improves the breakdown voltage （BV）. The BISJ LDMOS exhibits a BV of 300 V and Ron,sp of 8.08 mΩ·cm2 which increases BV by 35% and reduces Ron,sp by 60% compared with those of a conventional LDMOS with a drift length of 15 μm, respectively.