Comparative study of low frequency noise and hot-carrier reliability in SiGe PD SOI pMOSFETs

The stress effect of SiGe pMOSFETs has been investigated to understand the electrical properties of devices fabricated on the Si bulk and PD SOI substrates. A comparison of the drain saturation current (I_D.sat) and maximum transconductance (g_m,max) in both the SiGe bulk and the SiGe PD SOI devices clearly shows that the SiGe PD SOI is more immune from hot-carriers than the SiGe bulk. The stress-induced leakage current (SILC) is hardly detectable in ultra-thin oxide, because the increasing contribution of direct tunneling is comparable to the trap-assisted component. The SiGe PD SOI revealed degraded properties being mainly associated with the detrimental silicon-oxide interface states of the SOI structure.     

背栅效应对SOI横向高压器件击穿特性的影响

提出一种SOI基背栅体内场降低BG REBULF(back-gate reduced BULk field)耐压技术. 其机理是背栅电压诱生界面电荷，调制有源区电场分布，降低体内漏端电场，提高体内源端电场，从而突破习用结构的纵向耐压限制，提高器件的击穿电压. 借助二维数值仿真，分析背栅效应对厚膜高压SOI LDMOS (>600V) 击穿特性的影响，在背栅电压为330V时，实现器件击穿电压1020V，较习用结构提高47.83%. 该技术的提出，为600V以上级SOI基高压功率器件和高压集成电路的实现提供了一种新的设计思路. 关键词： SOI 背栅 体内场降低 LDMOS     

新型SOANN埋层SOI器件的自加热效应研究

本文提出了一个新型的SOI埋层结构SOANN (silicon on aluminum nitride with nothing),用AlN代替传统的SiO₂材料,并在SOI埋氧化层中引入空洞散热通道. 分析了新结构SOI器件的自加热效应.研究结果表明:用AlN做为SOI埋氧化层的材料, 降低了晶格温度,有效抑制了自加热效应.埋氧化层中的空洞,可以进一步提供散热通道, 使埋氧化层的介电常数下降,减小了电力线从漏端通过埋氧到源端的耦合, 有效抑制了漏致势垒降低DIBL(drain Induced barrier lowering)效应.因此,本文提出的新型SOANN结构可以提高SOI器件的整体性能,具有优良的可靠性.     

超短沟道绝缘层上硅平面场效应晶体管中热载流子注入应力导致的退化对沟道长度的依赖性

随着场效应晶体管(MOSFET)器件尺寸的进一步缩小和器件新结构的引入, 学术界和工业界对器件中热载流子注入(hot carrier injections, HCI)所引起的可靠性问题日益关注. 本文研究了超短沟道长度(L=30–150 nm)绝缘层上硅(silicon on insulator, SOI)场效应晶体管在HCI应力下的电学性能退化机理. 研究结果表明, 在超短沟道情况下, HCI 应力导致的退化随着沟道长度变小而减轻. 通过研究不同栅长器件的恢复特性可以看出, 该现象是由于随着沟道长度的减小, HCI应力下偏压温度不稳定性效应所占比例变大而导致的. 此外, 本文关于SOI器件中HCI应力导致的退化和器件栅长关系的结果与最近报道的鳍式场效晶体管(FinFET)中的结果相反. 因此, 在超短沟道情况下, SOI平面MOSFET器件有可能具有比FinFET器件更好的HCI可靠性.     

三维H形栅SOINMOS器件总剂量条件下的单粒子效应

本文通过数值模拟研究了H形栅SOI NMOS器件在总剂量条件下的单粒子效应. 首先通过分析仿真程序中影响迁移率的物理模型, 发现通过修改了的由于表面散射造成迁移率退化的Lombardi模型, 仿真的SOI晶体管转移特性和实测数据非常符合. 然后使用该模型, 仿真研究了处于截止态 (V_D=5V) 的 H形栅SOI NMOS器件在总剂量条件下的单粒子效应. 结果表明: 随着总剂量水平的增加, 器件在同等条件的重离子注入下, 产生的最大漏极电流脉冲只是稍有增大, 但是漏极收集电荷随总剂量水平大幅增加. 关键词： 单粒子脉冲电流 漏极收集电荷 总剂量效应     

一种新的GaAs PHEMT器件可靠性评估方法研究

通过研究应力前后GaAs PHEMT器件电特性的测量，分析了GaAs PHEMT退化的原因，从实验中 得出高场下碰撞电离的电离率与器件沟道电场峰值的关系曲线.对高场下碰撞电离率的实验 曲线进行拟合，可以得到碰撞电离率与器件沟道电场峰值的量化关系，由此可以对GaAs PHE MT器件的电性能和可靠性进行改善和评估.进一步改进GaAs PHEMT的击穿电压，将需要严格 控制沟道中的碰撞电离. 关键词： 高电子迁移率晶体管 碰撞电离率 可靠性评估     

Weak avalanche multiplication in SiGe heterojunction bipolar transistors on thin film silicon-on-insulator

In this paper, we propose an analytical avalanche multiplication model for the next generation of SiGe silicon-on-insulator (SOI) heterojunction bipolar transistors (HBTs) and consider their vertical and lateral impact ionizations for the first time. Supported by experimental data, the analytical model predicts that the avalanche multiplication governed by impact ionization shows kinks and the impact ionization effect is small compared with that of the bulk HBT, resulting in a larger base-collector breakdown voltage. The model presented in the paper is significant and has useful applications in the design and simulation of the next generation of SiGe SOI BiCMOS technology.     

SOI全内反射型光波导电光开关模型研究

根据受抑全反射的光学隧道效应和Ｇｏｏｓ－Ｈａｎｃｈｅｎ位移分析ＳＯＩ全内反射型光波导开关中导模的传输和反射特性。在讨论等离子体色散效应，ｐ－ｎ结大注入效应的基础上，分析了全内反射光波导开关的电学性质。设计了该器件的结构以数和电学参数。     

Hot-Carrier Effects on Total Dose Irradiated 65 nm n-Type Metal-Oxide-Semiconductor Field-Effect Transistors

The influence of total dose irradiation on hot-carrier reliability of 65 nm n-type metal-oxide-semiconductor fieldeffect transistors(nMOSFETs) is investigated.Experimental results show that hot-carrier degradations on irradiated narrow channel nMOSFETs are greater than those without irradiation.The reason is attributed to radiation-induced charge trapping in shallow trench isolation(STI).The electric field in the pinch-off region of the nMOSFET is enhanced by radiation-induced charge trapping in STI,resulting in a more severe hot-carrier effect.     

Novel fast-switching LIGBT with P-buried layer and partial SOI

A novel silicon-on-insulator lateral insulated gate bipolar transistor(SOI LIGBT)is proposed in this paper.The proposed device has a P-type buried layer and a partial-SOI layer,which is called the BPSOI-LIGBT.Due to the electric field modulation effect generated by the P-type buried layer and the partial-SOI layer,the proposed structure generates two new peaks in the surface electric field distribution,which can achieve a smaller device size with a higher breakdown voltage.The smaller size of the device is beneficial to the fast switching.The simulation shows that under the same size,the breakdown voltage of the BPSOI LIGBT is 26%higher than that of the conventional partial-SOI LIGBT(PSOI LIGBT),and 84%higher than the traditional SOI LIGBT.When the forward voltage drop is 2.05 V,the turn-off time of the BPSOI LIGBT is 71%shorter than that of the traditional SOI LIGBT.Therefore,the proposed BPSOI LIGBT has a better forward voltage drop and turn-off time trade-off than the traditional SOI LIGBT.In addition,the BPSOI LIGBT effectively relieves the self-heating effect of the traditional SOI LIGBT.