一种基于延时和带宽约束的纳米级互连线优化模型

基于RLC互连线延时模型,通过缓冲器插入和改变互连线宽及线间距,提出了一种基于延时和带宽约束的互连功耗-缓冲器面积的乘积优化模型.基于90 nm,65 nm和45 nm CMOS工艺验证了互连线优化模型,在牺牲1/3和1/2的带宽的前提下,平均能够节省46%和61%的互连功耗,以及65%和83%的缓冲器面积,能应用于纳米级SOC的计算机辅助设计. 关键词： 纳米互连功耗 缓冲器面积 延时 带宽     

A novel low-swing interconnect optimization model with delay and bandwidth constraints

Interconnect power and repeater area are important in the interconnect optimization of nanometer scale integrated circuits.Based on the RLC interconnect delay model,by wire sizing,wire spacing and adopting low-swing interconnect technology,this paper proposed a power-area optimization model considering delay and bandwidth constraints simultaneously.The optimized model is verified based on 65-nm and 90-nm complementary metal-oxide semiconductor(CMOS) interconnect parameters.The verified results show that averages of 36% of interconnect power and 26% of repeater area can be saved under 65-nm CMOS process.The proposed model is especially suitable for the computer-aided design of nanometer scale systems-on-chip.     

考虑自热效应的互连线功耗优化模型

基于互连线的分布式功耗模型,考虑自热效应的同时采用非均匀互连线结构,提出了一种基于延时、带宽、面积、最小线宽和最小线间距约束的互连动态功耗优化模型.分别在90和65 nm互补金属氧化物半导体工艺节点下验证了功耗优化模型的有效性,在工艺约束下同时不牺牲延时、带宽和面积所提模型能够降低高达35％互连线功耗.该模型适用于片上网络构架中大型互连路由结构和时钟网络优化设计.     

基于双电源电压和双阈值电压的全局互连性能优化

基于双电源电压和双阈值电压技术,提出了一种优化全局互连性能的新方法.文中首先定义了一个包含互连延时、带宽和功耗等因素的品质因子用以描述全局互连特性,然后在给定延时牺牲的前提下,通过最大化品质因子求得优化的双电压数值用以节省功耗.仿真结果显示,在65 nm工艺下,针对5%,10%和20%的允许牺牲延时,所提方法相较于单电压方法可分别获得27.8%,40.3%和56.9%的功耗节省.同时发现,随着工艺进步,功耗节省更加明显.该方法可用于高性能全局互连的优化和设计. 关键词： 全局互连 双电源电压 双阈值电压 功耗     

考虑非均匀温度分布效应的缓冲器插入最优尺寸研究

基于非均匀温度分布效应对互连延时的影响, 提出了一种求解互连非均匀温度分布情况下的缓冲器最优尺寸的模型. 给出了非均匀温度分布情况下的RC互连延时解析表达式, 通过引入温度效应消除因子, 得出了最优插入缓冲器尺寸以使互连总延时最优. 针对90 nm和65 nm工艺节点, 对所提模型进行了仿真验证, 结果显示, 相较于以往同类模型, 本文所提模型由于考虑了互连非均匀温度分布效应, 更加准确有效, 且在保证互连延时最优的情况下有效地提高了芯片面积的利用.     

一种考虑硅通孔电阻-电容效应的三维互连线模型

硅通孔(TSV)是三维集成电路的一种主流技术.基于TSV寄生参数提取模型,对不同物理尺寸的TSV电阻-电容(RC)参数进行提取,采用Q3D仿真结果验证了模型精度.分析TSVRC效应对片上系统的性能及功耗影响,推导了插入缓冲器的三维互连线延时与功耗的解析模型.在45nm互补金属氧化物半导体工艺下,对不同规模的互连电路进行了比较分析.模拟结果显示,TSVRC效应导致互连延时平均增加10%,互连功耗密度平均提高21%;电路规模越小,TSV影响愈加显著.在三维片上系统前端设计中,包含TSV寄生参数的互连模型将有助于设计者更加精确地预测片上互连性能.     

Statistical Elmore delay of RC interconnect tree

As feature size keeps scaling down,process variations can dramatically reduce the accuracy in the estimation of interconnect performance.This paper proposes a statistical Elmore delay model for RC interconnect tree in the presence of process variations.The suggested method translates the process variations into parasitic parameter extraction and statistical Elmore delay evaluation.Analytical expressions of mean and standard deviation of interconnect delay can be obtained in a given fluctuation range of interconnect geometric parameters.Experimental results demonstrate that the approach matches well with Monte Carlo simulations.The errors of proposed mean and standard deviation are less than 1% and 7%,respectively.Simulations prove that our model is efficient and accurate.     

Three-dimensional global interconnect based on a design window

Based on a stochastic wire length distributed model, the interconnect distribution of a three-dimensional integrated circuit (3D IC) is predicted exactly. Using the results of this model, a global interconnect design window for a giga-scale system-on-chip (SOC) is established by evaluating the constraints of 1) wiring resource, 2) wiring bandwidth, and 3) wiring noise. In comparison to a two-dimensional integrated circuit (2D IC) in a 130-nm and 45-nm technology node, the design window expands for a 3D IC to improve the design reliability and system performance, further supporting 3D IC application in future integrated circuit design.     

一种基于纳米级CMOS工艺的互连线串扰RLC解析模型

基于纳米级CMOS工艺,综合考虑电容耦合与电感耦合效应,提出了分布式RLC耦合互连解析模型.采用函数逼近理论与降阶技术,在斜阶跃输入信号下提出了受扰线远端的数值表达式. 基于90和65 nm CMOS工艺,对不同的互连耦合尺寸下的分布式RLC串扰解析模型和Hspice仿真结果进行了比较,误差绝对值都在4%内,能应用于纳米级片上系统（SOC）的电子设计自动化（EDA）设计和集成电路优化设计. 关键词： 纳米级CMOS 互连串扰 分布式 RLC解析模型')" href="#">RLC解析模型     

A statistical RCL interconnect delay model taking account of process variations

As the feature size of the CMOS integrated circuit continues to shrink, process variations have become a key factor affecting the interconnect performance. Based on the equivalent Elmore model and the use of the polynomial chaos theory and the Galerkin method, we propose a linear statistical RCL interconnect delay model, taking into account process variations by successive application of the linear approximation method. Based on a variety of nano-CMOS process parameters, HSPICE simulation results show that the maximum error of the proposed model is less than 3.5%. The proposed model is simple, of high precision, and can be used in the analysis and design of nanometer integrated circuit interconnect systems.     

考虑互连温度分布的缓冲器插入延时优化方法

针对VLSI设计中存在的互连电感效应、热电耦合以及互连温度分布的问题,提出一种缓冲器插入延时优化方法.首先根据互连温度分布的特点得出其电阻模型和延时模型,通过延时、功耗和温度之间的热电耦合效应求得考虑互连温度分布的缓冲器插入最优化延时,利用Matlab软件求得最佳优化结果.采用该方法针对45 nm工艺节点的缓冲器插入进行分析和验证,证实了方法的有效性.研究表明,忽略互连电感效应会高估芯片的优化延时,忽略互连温度分布会低估芯片的优化延时,在全局互连尺寸较小(线宽为245 nm)时,忽略互连温度分布会低估互连延时8.71%.     

Size effect on the mechanical behaviour of polycrystalline copper microbeams

To reduce costs and to remain competitive in the worldwide electronics industry, semiconductor manufacturers continually miniaturize devices. Today, the interconnect lines linking electronic components have diameters of the order of 100?nm or smaller. At the nanometre scale, strong size effects modify the mechanical properties of materials. To examine such effects, freestanding microbeams with geometrical and microstructural properties similar to those of interconnect lines have been designed. The yield stress dependence of the microbeams on their microstructure, shape and dimensions was investigated. As predicted by the Hall–Petch law, an increase in the yield stress with a decrease in the grain size was observed. In addition, a decrease in the cross-section of the microbeams at a fixed grain size led to a decrease in the yield stress. Hence, the yield domain of interconnect lines was observed to be controlled by two competitive size effects. This result imposes some restrictions on the design of electronic devices.     

室内直达与非直达环境无线传播综合信道建模

本文主要针对室内无线传播信道直达(line of sight, LOS)与非直达(no line of sight, NLOS)环境, 引入参考模型研究其建模设计及其相关统计特性. 文中提出了一种基于几何散射模型的综合改进室内参考信道模型, 假设将无限数量的散射体均匀分布在三维空间的一个二维(two dimensional, 2D)水平面上. 本文推导了电磁波达信号到达角(angle of arrival, AOA) 概率分布函数(probability density function, PDF)、多普勒功率谱密度(power spectral Density, PSD)、 时间自相关函数(autocorrelation function, ACF)的解析表达式, 并分析其重要参数对函数的影响. 此外, 本文还通过非现实参考模型提出了一种高效的SOC(Sum of Cisoids) 信道仿真模型, 同时提出了设计SOC信道仿真模型的两种有效参数计算方法, 并比较两者的计算性能. 仿真结果表明, 信道仿真模型的统计特性与参考模型相匹配, 即室内参考模型可以通过的SOC信道仿真模型来近似, 同时信道仿真模型可以很好的应用于评估室内无线通信系统的性能, 拓宽了室内无线信道建模的研究, 同时减少实现开支.     

架空及埋地多导体线缆对HEMP辐照的瞬态响应

针对瞬态电磁场辐照多导体电缆问题,首先介绍了一种用于计算架空及埋地线缆瞬态响应的高效时域宏模型。该模型基于传输线理论,利用广义特征线法和SPICE求解器中集成的模拟行为建模库,在时域内实现建模过程中涉及的频率相关参数和卷积计算。该方法适用性广泛,可同时用于架空及埋地线缆的场线耦合建模仿真;与现有时域有限差分法相比,不需要对时间和空间进行离散,以及对频率相关参数进行矢量匹配或数值逆傅里叶变换,因此可简化建模步骤,提高建模及仿真计算的效率;该宏模型计算效率不受线缆长度限制,适用于研究多导体长距离线缆。其次,在时域和频域分别研究了高空电磁脉冲(HEMP)的环境及特点。最后,利用算例验证了所提宏模型计算架空及埋地线缆响应的有效性,并利用该方法分别研究了架空地线对三相输电线路瞬态响应的影响以及埋地电力电缆金属护套在端接线性及非线性保护器件时对HEMP的瞬态响应。结果表明,宏模型法可在时域内高效地计算入射场耦合架空输电线及埋地电力电缆的瞬态响应,特别是对于带有非线性器件的长多导体线缆。     

An Interconnect Bus Power Optimization Method

A simple yet accurate interconnect parasitical capacitance model is presented. Based on this model a novel interconnect bus optimization methodology is proposed. Combining wire spacing with wire ordering, this methodology focuses on bus dynamic power optimization with consideration of bus performance requirements. The optimization methodology is verified under a 65 nm technology node and it shows that with 50% slack in the routing space, a 33.039% power saving can be provided by the proposed optimization methodology for an intermediate video bus compared to the 27.68% power saving provided by uniform spacing technology. The proposed methodology is especially suitable for computer-aided design of nanometer scale on-chip buses.     

基于双缝隙结构的电光调制器设计与工艺实现

受铜线带宽小、延时大、功耗高的限制,下一代芯片互连较为可行的一种解决方式是采用光互连.调制器作为其中的关键器件,有重要的研究意义.设计了一种新型的硅基双缝隙波导电光调制器,该调制器结构采用法布里-珀罗微谐振器,依靠缝隙内高非线性聚合物的快速电光效应,通过外加电压达到调制效果.调制器结构包含了新型的一般微纳波导到双缝隙波...     

一种考虑温度的分布式互连线功耗模型

基于集总式电阻-电容树形功耗模型,考虑了非均匀温度分布对互连线电阻的影响,提出了一种新的分布式互连线动态功耗解析模型,解决了集总式模型不能表征非均匀温度变化带来的电阻变化的问题,并计算了一次非理想的激励冲激下整个互连模型消耗的总能量.基于所提出的分布式互连线功耗模型,计算了纳米级互补金属氧化物半导体（CMOS）工艺典型长度互连线的Elmore延时和功耗,发现非均匀温度分布对互连功耗的影响随着互连线长度的增加而增加,单位长度功耗随着CMOS工艺特征尺寸的变化而基本不变.文中所提出的功耗模型可以用来精确估算互 关键词： 互连线 温度梯度 动态功耗模型 纳米级互补金属氧化物半导体     

An interconnecting bus power optimization method combining interconnect wire spacing with wire ordering

On-chip interconnect buses consume tens of percents of dynamic power in a nanometer scale integrated circuit and they will consume more power with the rapid scaling down of technology size and continuously rising clock frequency, therefore it is meaningful to lower the interconnecting bus power in design. In this paper, a simple yet accurate interconnect parasitic capacitance model is presented first and then, based on this model, a novel interconnecting bus optimization method is proposed. Wire spacing is a process for spacing wires for minimum dynamic power, while wire ordering is a process that searches for wire orders that maximally enhance it. The method, i.e., combining wire spacing with wire ordering, focuses on bus dynamic power optimization with a consideration of bus performance requirements. The optimization method is verified based on various nanometer technology parameters, showing that with 50% slack of routing space, 25.71% and 32.65% of power can be saved on average by the proposed optimization method for a global bus and an intermediate bus, respectively, under a 65-nm technology node, compared with 21.78% and 27.68% of power saved on average by uniform spacing technology. The proposed method is especially suitable for computer-aided design of nanometer scale on-chip buses.     

Comparative analysis of long-haul system based on SSB modulation utilising dual parallel Mach–Zehnder modulators

In this paper, we have proposed a long-haul optical transmission system, based on a single sideband (SSB) modulation scheme. Analytical and simulation models have been developed, optimised and demonstrated for the proposed SSB system configurations. The SSB modulation scheme was proposed to overcome dispersion in the fibre. We have shown that the related link losses can be minimized by increasing the quality of the optical signal at the modulation. We have optimised the radio over fibre configuration scheme based on dual parallel dual drive Mach–Zehnder Modulator, thereby increasing transmission length of the fibre. With the proposed SSB, by suppressing some of the harmonics and cancelling one of the sidebands, we have halved the RF power fading and interference. The developed analytical (theoretical/mathematical) model agrees very well with the simulation results using two (both) different commercial simulation tools. The optical signal is boosted while minimizing the number of repeaters. We report a SSB configuration, compensation and amplification with individual spans of 150 km, by extending the length of the link up to 3250 km. The proposed system configuration exhibits high performance with less complexity and lower cost.     

基于RLCπ型等效模型的互连网络精确焦耳热功耗计算

基于互连网络的RLC π型等效模型,考虑电感的屏蔽作用和非理想的阶跃激励,提出了互连线网络在斜阶跃激励下的焦耳热功耗计算方法,极大地简化了互连网络中电流和功耗的表达式. 基于90 nm金属氧化物半导体(CMOS)工艺的互连参数对所提出的计算方法进行了计算和仿真验证,对于上升信号小于1 ns的情况,计算结果与Hspice仿真结果的误差小于3%,具有很高的精度,适合应用于大规模互连网络中的功耗估算和热分析.