一种应用于激光雷达接收机的回波峰值检测量化电路

为实现对激光雷达回波峰值的测量,介绍了一种应用于激光雷达接收机的回波峰值检测量化电路,采用对电压回波脉冲采样保持的方法配合低速模拟数字转换器(Analog to Digital Converter,ADC)来实现回波峰值的高精度量化。电路采用SMIC 0.18μm工艺设计,仿真结果显示,该电路采样电压动态范围为800 mV,采样3 ns脉宽的脉冲保持电压误差小于3.16%,实现10 bit的量化精度。整体电路采样周期由外部使能信号和复位信号控制,可满足不同场合下激光雷达接收机回波峰值采样的应用需求。     

基于光斑跟踪器的脉冲峰值保持电路的实现

针对激光光斑跟踪器接收信号处理系统中常规A/D采样电路对脉冲电压峰值采集的技术要求,设计了一种脉冲峰值保持电路。通过对该峰值保持电路的各项指标进行理论分析,采用宽带宽跨导放大器MAX436设计该峰值保持电路,并对该电路进行了仿真分析与实验研究,得到满足参数指标设计要求的实验结果:对于脉宽50 ns的激光脉冲信号,在输入信号幅度大于100 mV时,峰值保持电路的响应速度2 ns,下垂速率6.0 mV/s,保持精度1.1%。     

亚RS激光脉冲电取样方法

针对亚ns激光脉冲,提出一种基于ps脉冲传输线和高速电子电路的电快脉冲取样方法,设计了选通脉冲产生电路和高速取样保持电路,给出一种提高实时采样速率的交叉采样方法,该方法由并联结构的多组取样门阵列实现。可应用于多路激光脉冲的精密测量。     

亚ns激光脉冲电取样方法

 针对亚ns激光脉冲,提出一种基于ps脉冲传输线和高速电子电路的电快脉冲取样方法,设计了选通脉冲产生电路和高速取样保持电路,给出一种提高实时采样速率的交叉采样方法,该方法由并联结构的多组取样门阵列实现。可应用于多路激光脉冲的精密测量。     

基于2-6GHz的两级分布式超宽带低噪声放大器设计

针对超宽带无线通信系统应用设计实现了一个2-6GHz的两级分布式CMOS低噪声放大器(LNA)。采用分布式放大器结构既能扩展带宽,又能保证电路具有低噪声、良好的反向隔离度和平坦增益的特性。利用ADS仿真软件对整个电路进行仿真优化设计,电路仿真结果表明:在2-6GHz频率范围内增益(S21)保持26.506±0.961d B平坦增益,噪声系数(NF)为0.849±0.238d B,输入回波损耗(S11)小于-18.338d B。     

高精度石英加速度计自适应采集系统设计

为了保证高精度石英加速度计输出精度,采用将加速度计输出分段的方式设计了一个高精度数据采集电路;首先,通过切换采样电阻对不同输出段信号进行采样;其次,设计了低通滤波器进行滤波;然后,进行了包括跨阻放大、低通滤波器、电源的详细电路设计以及关键元器件的选择;最后,进行仿真实验验证;结果显示该方法既充分利用A/D芯片的量程,保证精度,又能满足宽量程要求;采集电路最低精度在±8×10-5g以内,最高精度在±10-5g以内,满足高精度惯性导航的需要。     

天文观测相机低噪声CCD视频处理电路的分析与设计

在讨论天文观测相机低噪声视频处理电路的基础上,对前置放大、差分放大、可编程增益放大、相关双采样及16bit模数转换等关键组成部分进行了分析,给出各组成部分的设计方法。对所设计的低噪声视频处理电路进行了PSPICE仿真和实验测试,仿真和实验结果表明,该视频处理电路在本身引入噪声较小的同时,有效地抑制了CCD的复位噪声和1/f等低频噪声,使天文观测相机的整机噪声<15e-,达到了指标要求。     

基于相关双采样的线阵CCD信号采集电路设计

针对CCD信号相关双采样（CDS）难于实现的问题,介绍了一种简单实用、易于实现的线阵CCD信号相关双采样电路。该电路采用CPLD、AD9844实现了线阵CCD时序驱动、信号相关双采样、自动增益、A／D转换等一体化设计。实验表明,设计的采集电路能有效地消除复位等多种噪声的影响,实现对背景光的自适应调整,达到提高信噪比,改善视频图像的目的。     

大参数周期信号随机共振解析

通过调节双稳系统参数实现大参数频率范围内周期信号的随机共振, 在工程上具有重要意义. 推导了双稳系统参数的归一化变换, 利用归一化变换原理对大参数周期信号的随机共振进行了数值仿真, 阐明该原理适用于任意频率周期信号. 对大参数随机共振用电路模拟进行了实验验证, 揭示了通过调节双稳系统参数可以实现大参数频率范围内的随机共振. 分析了二次采样实现大参数周期信号随机共振的机理, 通过数值仿真与参数归一化变换方法进行了比较. 仿真结果表明, 在输入信号幅度变化的情况下, 二次采样方法易出现发散现象, 而归一化变换具有更好的稳定性与适应性.     

一种新型高速光保持模块

针对光电混合模数转换系统中采样光脉冲很窄,高速积分保持电路实现较困难这一问题,本文提出了一种新型的高速光保持模块.通过使用多个耦合器组成的无源结构,将采样后的超窄光脉冲转换成一族脉冲簇,再经过光电转换和电低通滤波,得到了顶部较平、脉宽较宽的脉冲,有助于降低后续处理电路的复杂度.实验结果表明,这种结构能够较好地实现将超窄脉冲展宽成平顶宽脉冲的功能.     

Simple Analog Complementary Metal Oxide Semiconductor Circuit for Generating Motion Signal

We proposed in this study a novel analog complementary metal oxide semiconductor (CMOS) circuit for generating a motion signal when an object moves, which is a simple structure. The proposed unit circuit was constructed using a previously proposed edge detection circuit and a novel proposed circuit for generating a motion signal which accepts an edge signal. The part for generating the motion signal was constructed using six metal oxide semiconductor (MOS) transistors and one capacitor. Results obtained by the simulation program with integrated circuit emphasis (SPICE) and the measured results of a test circuit constructed with discrete MOS transistors and the test circuit fabricated with a 1.2 μm CMOS process showed that the proposed unit circuit can output pulsed current (motion signal) when an object moves on the circuit. It was clarified from the SPICE results that the two-dimensional network constructed with proposed unit circuits can output motion signals. The size of the novel unit circuit is expected to be about 110 × 110μm² obtained by the 1.2 μm CMOS process. It is possible to arrange 90 × 90 unit circuits on a chip which has an area of 1 × 1cm². The aperture ratio is expected to be about 21%, which is twice as large as that of the previously proposed circuit. An integrated circuit for image processing in real time can thus be realized by applying the two-dimensional network constructed with the proposed circuits.     

Heterogeneous integration of GaAs pHEMT and Si CMOS on the same chip

In this work,we demonstrate the technology of wafer-scale transistor-level heterogeneous integration of Ga As pseudomorphic high electron mobility transistors(p HEMTs) and Si complementary metal–oxide semiconductor(CMOS) on the same Silicon substrate.Ga As p HEMTs are vertical stacked at the top of the Si CMOS wafer using a wafer bonding technique,and the best alignment accuracy of 5 μm is obtained.As a circuit example,a wide band Ga As digital controlled switch is fabricated,which features the technologies of a digital control circuit in Si CMOS and a switch circuit in Ga As p HEMT,15% smaller than the area of normal Ga As and Si CMOS circuits.     

The effect of body bias of the metal-oxide-semiconductor field-effect transistor in the resistive network on spatial current distribution in a bio-inspired complementary metal-oxide-semiconductor vision chip

Complementary metal-oxide-semiconductor (CMOS) vision chips for edge detection based on a resistive circuit have recently been developed. These chips help in the creation of neuromorphic systems of a compact size, high speed of operation, and low power dissipation. The output of the vision chip depends predominantly upon the electrical characteristics of the resistive network which consists of a resistive circuit. In this paper, the body effect of the metal-oxide-semiconductor field-effect transistor for current distribution in a resistive circuit is discussed with a simple model. In order to evaluate the model, two 160 × 120 CMOS vision chips have been fabricated using a standard CMOS technology. The experimental results nicely match our prediction.     

Ultrafast All-Optical Serial-to-Parallel Conversion and Its Application to Optical Label Processing

A novel scheme for all-optical serial-to-parallel conversion (SPC) is proposed for label recognition of ultrafast asynchronous burst optical packets. Compact SP converter modules were developed using a fiber array or a surfaceemitting planar lightwave circuit, and 1-Tbit/s and 40-Gbit/s SPC for 16-bit optical packets is demonstrated using the modules. The key device in the converter is a spin-polarized surface-reflection all-optical switch (LOTOS) with an ultrafast switching time (250 fs) and an extremely high on/off ratio (>30 dB). Label recognition of 40-Gbit/s 16-bit burst-mode optical packets is experimentally confirmed using an optical clock-pulse generator and a complementary metal-oxide-semiconductor (CMOS) electronics circuit as well as the all-optical SP converter. 1 x 4 self-routing is also demonstrated using 2-channel control signals generated from the CMOS circuit according to a routing table.     

CMOS反相器的电磁干扰频率效应

利用自主开发的2维半导体器件-电路联合仿真器,研究了CMOS反相器在1 MHz～20 GHz电磁干扰作用下的响应。仿真结果表明:低频电磁干扰通过控制CMOS反相器中MOS管的导通、截止影响CMOS反相器的正常工作;高频电磁干扰通过MOS管中的本征电容耦合到输出端,干扰CMOS反相器的工作状态;CMOS反相器对于电磁干扰的敏感度随着干扰频率上升而不断降低。     

Theoretical analysis and experimental application of CDS CMOS integrated circuit for uncooled infrared focal plane arrays

In this paper, a typical correlated double sampling (CDS) complementary metal oxide semiconductor (CMOS) circuit for uncooled infrared focal plane array (IRFPA) is theoretically analyzed, the key factor of CDS CMOS integrated circuit is pointed out, and a new CDS integrated circuit which is high correlative for low-frequency noise is applied in an experimental readout chip for uncooled IRFPA. Theoretical analysis indicates that the sample transfer function of a noise source acted on by CDS processing is related to noise frequency and sampling time interval and the key factor of CDS circuit for reducing or eliminating noise in readout integrated circuit is the sampling time interval. The experimental readout chip with high noise-correlative CDS integrated circuit is fabricated to verify the theoretical analysis, which can be applied to uncooled IRFPAs.     

A 128 × 128 Pixel Complementary Metal Oxide Semiconductor Image Sensor with an Improved Pixel Architecture for Detecting Modulated Light Signals

A complementary metal oxide semiconductor (CMOS) image sensor for the detection of modulated light under background illumination has been developed. When an object is illuminated by a modulated light source under background illumination the sensor enables the object alone to be captured. This paper describes improvements in pixel architecture for reducing fixed pattern noise (FPN) and improving the sensitivity of the image sensor. The improved 128 × 128 pixel CMOS image sensor with a column parallel analog-to-digital converter (ADC) circuit was fabricated using 0.35-mm CMOS technology. The resulting captured images are shown and the properties of improved pixel architecture are described. The image sensor has FPN of 1/28 that of the previous image sensor and an improved pixel architecture comprising a common in-pixel amp and a correlated double sampling (CDS) circuit. The use of a split photogate increases the sensitivity of the image sensor to 1.3 times that of the previous image sensor.     

A New CMOS Read-out IC for Uncooled Microbolometer Infrared Image Sensor

An uncooled microbolometer image sensor, used in an IR image sensor, is made by a micro electro mechanical systems (MEMS) process, so the value of the microbolometer resistor has a process variation. Also, the reference resistor, which is used to connect to the microbolometer, is fabricated by a standard CMOS process, and the difference between the values of the microbolometer resistor and the reference resistor generates an unwanted output signal for the same input from the sensor array. In order to minimize this problem, a new CMOS read-out integrated circuit (ROIC) was designed. Instead of a single input mode, a differential input mode scheme and a simple method to compensate the resistor value are proposed. Using results from a computer simulation, it is observed that the output characteristic of the ROIC was improved and the effect of the process variation was decreased without using complex compensation circuits. Based on the simulation results, a prototype device including an ROIC that was fabricated by a standard 0.25um CMOS process and a microbolometer with a 16 x 16 sensor array was fabricated and characterized.     

Optimization of fat tree encoder for ultra high speed analog to digital converter using 45 nanometer technology

The design of high speed, compact and low power fat tree encoder circuits using static CMOS gates is presented. In this paper, we propose a modified 3 bit fat tree encoder (FTE) that can operate in high frequency without a sophisticated circuit structure. In addition, the technique of hardware sharing is adopted in this design to reduce the number of transistors. The study uses complementary metal oxide semiconductor (CMOS) 45 nm-technology. The proposed static design has improved delay and power compared to a conventional ROM encoder circuit implementation. The simulation result indicates that it functions successfully and works at 200-MHz speed. The average power consumption of the circuit under room temperature is 20.7 nW. The total core area is 0.011 mm². As expected, the proposed design can be easily integrated in various kind of digital application.     

基于CMOS图像传感器的成像系统设计

以OV 5 116CMOS图像传感器为例 ,讨论了基于CMOS图像传感器的成像系统的电路设计方法及系统设计中应注意的问题 ;并通过对CMOS图像传感器外围电路的优化设计实现了成像系统的微型化和轻量化。