共查询到18条相似文献,搜索用时 156 毫秒
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针对VLSI设计中存在的互连电感效应、热电耦合以及互连温度分布的问题,提出一种缓冲器插入延时优化方法.首先根据互连温度分布的特点得出其电阻模型和延时模型,通过延时、功耗和温度之间的热电耦合效应求得考虑互连温度分布的缓冲器插入最优化延时,利用Matlab软件求得最佳优化结果.采用该方法针对45 nm工艺节点的缓冲器插入进行分析和验证,证实了方法的有效性.研究表明,忽略互连电感效应会高估芯片的优化延时,忽略互连温度分布会低估芯片的优化延时,在全局互连尺寸较小(线宽为245 nm)时,忽略互连温度分布会低估互连延时8.71%. 相似文献
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硅通孔(TSV)是三维集成电路的一种主流技术.基于TSV寄生参数提取模型,对不同物理尺寸的TSV电阻-电容(RC)参数进行提取,采用Q3D仿真结果验证了模型精度.分析TSVRC效应对片上系统的性能及功耗影响,推导了插入缓冲器的三维互连线延时与功耗的解析模型.在45nm互补金属氧化物半导体工艺下,对不同规模的互连电路进行了比较分析.模拟结果显示,TSVRC效应导致互连延时平均增加10%,互连功耗密度平均提高21%;电路规模越小,TSV影响愈加显著.在三维片上系统前端设计中,包含TSV寄生参数的互连模型将有助于设计者更加精确地预测片上互连性能. 相似文献
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基于集总式电阻-电容树形功耗模型,考虑了非均匀温度分布对互连线电阻的影响,提出了一种新的分布式互连线动态功耗解析模型,解决了集总式模型不能表征非均匀温度变化带来的电阻变化的问题,并计算了一次非理想的激励冲激下整个互连模型消耗的总能量.基于所提出的分布式互连线功耗模型,计算了纳米级互补金属氧化物半导体(CMOS)工艺典型长度互连线的Elmore延时和功耗,发现非均匀温度分布对互连功耗的影响随着互连线长度的增加而增加,单位长度功耗随着CMOS工艺特征尺寸的变化而基本不变.文中所提出的功耗模型可以用来精确估算互
关键词:
互连线
温度梯度
动态功耗模型
纳米级互补金属氧化物半导体 相似文献
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基于非均匀温度分布效应对互连延时的影响, 提出了一种求解互连非均匀温度分布情况下的缓冲器最优尺寸的模型. 给出了非均匀温度分布情况下的RC互连延时解析表达式, 通过引入温度效应消除因子, 得出了最优插入缓冲器尺寸以使互连总延时最优. 针对90 nm和65 nm工艺节点, 对所提模型进行了仿真验证, 结果显示, 相较于以往同类模型, 本文所提模型由于考虑了互连非均匀温度分布效应, 更加准确有效, 且在保证互连延时最优的情况下有效地提高了芯片面积的利用. 相似文献
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A novel interconnect-optimal repeater insertion model with target delay constraint in 65nm CMOS 下载免费PDF全文
Repeater optimization is the key for SOC (System on Chip)
interconnect delay design. This paper proposes a novel optimal model
for minimizing power and area overhead of repeaters while meeting
the target performance of on-chip interconnect lines. It also
presents Lagrangian function to find the number of repeaters and
their sizes required for minimizing area and power overhead with
target delay constraint. Based on the 65 nanometre CMOS technology,
the computed results of the intermediate and global lines show that
the proposed model can significantly reduce area and power of
interconnected lines, and the better performance will be achieved
with the longer line. The results compared with the reference paper
demonstrate the validity of this model. It can be integrated into
repeater design methodology and CAD (computer aided design) tool for
interconnect planning in nanometre SOC. 相似文献
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A simple yet accurate interconnect parasitical capacitance model is presented. Based on this model a novel interconnect bus optimization methodology is proposed. Combining wire spacing with wire ordering, this methodology focuses on bus dynamic power optimization with consideration of bus performance requirements. The optimization methodology is verified under a 65 nm technology node and it shows that with 50% slack in the routing space, a 33.039% power saving can be provided by the proposed optimization methodology for an intermediate video bus compared to the 27.68% power saving provided by uniform spacing technology. The proposed methodology is especially suitable for computer-aided design of nanometer scale on-chip buses. 相似文献
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Interconnect power and repeater area are important in the interconnect optimization of nanometer scale integrated circuits.Based on the RLC interconnect delay model,by wire sizing,wire spacing and adopting low-swing interconnect technology,this paper proposed a power-area optimization model considering delay and bandwidth constraints simultaneously.The optimized model is verified based on 65-nm and 90-nm complementary metal-oxide semiconductor(CMOS) interconnect parameters.The verified results show that averages of 36% of interconnect power and 26% of repeater area can be saved under 65-nm CMOS process.The proposed model is especially suitable for the computer-aided design of nanometer scale systems-on-chip. 相似文献
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Drain-induced barrier lowering effect for short channel dual material gate 4H silicon carbide metal—semiconductor field-effect transistor 下载免费PDF全文
Sub-threshold characteristics of the dual material gate 4H-SiC MESFET (DMGFET) are investigated and the analytical models to describe the drain-induced barrier lowering (DIBL) effect are derived by solving one- and two- dimensional Poisson’s equations. Using these models, we calculate the bottom potential of the channel and the threshold voltage shift, which characterize the drain-induced barrier lowering (DIBL) effect. The calculated results reveal that the dual material gate (DMG) structure alleviates the deterioration of the threshold voltage and thus suppresses the DIBL effect due to the introduced step function, which originates from the work function difference of the two gate materials when compared with the conventional single material gate metal-semiconductor field-effect transistor (SMGFET). 相似文献
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为了减小馈线损耗和方便天线旋转,设计了超宽带Cassegrain双反射面天线系统。采用FEKO数值模拟软件在0.2~1.5 GHz频率范围内模拟了不同副反射面直径的4.5 m双反射面天线(焦径比为0.4)的辐射增益,并与相同口径和焦径比的前馈式反射面天线进行了比较。模拟结果表明:当双曲副反射面直径为70 cm,焦距为22.5 cm时,在0.2~1.0 GHz频率范围内,双反射面天线增益比前馈式抛物面天线高1~2 dB;在1.1~1.5 GHz频率范围内,双反射面天线增益比前馈式抛物面天线小1~2 dB。选择直径为70 cm、焦距为22.5 cm的双曲副面与TEM喇叭和4.5 m抛物面组成双反射面天线系统,分别用960 ps和3 ns脉宽的单极脉冲源对天线进行了实验研究。实验结果表明:用960 ps和3 ns脉宽的单极脉冲激励,Cassegrain双反射面天线在70 m轴上远场辐射场波形峰峰值分别为前馈式反射面天线的158%和162%。 相似文献
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An interconnecting bus power optimization method combining interconnect wire spacing with wire ordering 下载免费PDF全文
On-chip interconnect buses consume tens of percents of dynamic power in a nanometer scale integrated circuit and they will consume more power with the rapid scaling down of technology size and continuously rising clock frequency, therefore it is meaningful to lower the interconnecting bus power in design. In this paper, a simple yet accurate interconnect parasitic capacitance model is presented first and then, based on this model, a novel interconnecting bus optimization method is proposed. Wire spacing is a process for spacing wires for minimum dynamic power, while wire ordering is a process that searches for wire orders that maximally enhance it. The method, i.e., combining wire spacing with wire ordering, focuses on bus dynamic power optimization with a consideration of bus performance requirements. The optimization method is verified based on various nanometer technology parameters, showing that with 50% slack of routing space, 25.71% and 32.65% of power can be saved on average by the proposed optimization method for a global bus and an intermediate bus, respectively, under a 65-nm technology node, compared with 21.78% and 27.68% of power saved on average by uniform spacing technology. The proposed method is especially suitable for computer-aided design of nanometer scale on-chip buses. 相似文献
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Silicon carbide (SiC) based metal semiconductor field effect transistor (MESFET) is fabricated by using a standard SiC MESFET structure with the application of a dual p-buffer layer and a multi-recessed gate to the process for S-band power amplifier. The lower doped upper-buffer layer serves to maintain the channel current, while the higher doped lower-buffer layer is used to provide excellent electron confinement in the channel layer. A 20-mm gate periphery SiC MESFET biased at a drain voltage of 85 V demonstrates a pulsed wave saturated output power of 94 W, a linear gain of 11.7 dB, and a maximum power added efficiency of 24.3% at 3.4 GHz. These results are improved compared with those of the conventional single p-buffer MESFET fabricated in this work using the same process. A radio-frequency power output greater than 4.7 W/mm is achieved, showing the potential as a high-voltage operation device for high-power solid-state amplifier applications. 相似文献
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在飞机、舰艇、装甲、汽车电子控制系统中采用双余度发动机状态监测技术,能够有效提高飞机、舰艇、装甲、汽车运行的安全性和可靠性,以某型涡轴发动机为研究对象,对双余度发动机状态监测技术进行了深入研究,研制了双余度发动机状态监测系统,介绍了系统的总体设计、软硬件设计、余度设计,虚拟仪表设计,并在双余度发动机状态监测系统的设计中引入了嵌入式PC/104模块;为了使状态监测系统具有更好的扩展性和适应性,将系统设计成可以在两种方式下工作:机载运行方式和地面试车方式,通过这两种方式对发动机状态进行自动监测,为发动机的状态趋势分析、故障诊断和视情维修提供科学的依据;采用双余度发动机状态监测技术研制的某型涡轴发动机状态实时监测系统经过了大量的地面试验和某型直升机上试飞试验,功能、性能满足要求,目前该系统已在某型直升机上得到应用。 相似文献