共查询到17条相似文献,搜索用时 187 毫秒
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提出了同时考虑通孔效应和边缘传热效应的互连线温度分布模型,获得了适用于单层互连线和多层互连线温度分布的解析模型,并基于65 nm互补金属氧化物半导体(CMOS)工艺参数计算了不同长度单层互连线和多层互连线的温度分布.对于单层互连线,考虑通孔效应后中低层互连线的温升非常低,而全局互连线几乎不受通孔效应的影响,温升仍然很高.对于多层互连线,最上层互连线的温升最高,温升和互连介质层厚度近似成正比,而且互连介质材料热导率越低,温升越高.所提出的互连线温度分布模型,能应用于纳米级CMOS计算机辅助设计.
关键词:
通孔效应
边缘传热效应
纳米级互连线
温度分布模型 相似文献
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基于纳米级CMOS工艺,综合考虑电容耦合与电感耦合效应,提出了分布式RLC耦合互连解析模型.采用函数逼近理论与降阶技术,在斜阶跃输入信号下提出了受扰线远端的数值表达式. 基于90和65 nm CMOS工艺,对不同的互连耦合尺寸下的分布式RLC串扰解析模型和Hspice仿真结果进行了比较,误差绝对值都在4%内,能应用于纳米级片上系统(SOC)的电子设计自动化(EDA)设计和集成电路优化设计.
关键词:
纳米级CMOS
互连串扰
分布式
RLC解析模型')" href="#">RLC解析模型 相似文献
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硅通孔(TSV)是三维集成电路的一种主流技术.基于TSV寄生参数提取模型,对不同物理尺寸的TSV电阻-电容(RC)参数进行提取,采用Q3D仿真结果验证了模型精度.分析TSVRC效应对片上系统的性能及功耗影响,推导了插入缓冲器的三维互连线延时与功耗的解析模型.在45nm互补金属氧化物半导体工艺下,对不同规模的互连电路进行了比较分析.模拟结果显示,TSVRC效应导致互连延时平均增加10%,互连功耗密度平均提高21%;电路规模越小,TSV影响愈加显著.在三维片上系统前端设计中,包含TSV寄生参数的互连模型将有助于设计者更加精确地预测片上互连性能. 相似文献
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针对InGaAs单光子雪崩光电二极管(SPAD)的光电感应特性,研究了基于门控主动式淬灭的SPAD动态偏置控制和电路实现的策略.采用门控主动淬灭控制可降低淬灭时间,有效抑制暗计数和后脉冲效应.接口感应检测电路采用标准互补金属氧化物半导体(CMOS)工艺进行制造,而SPAD则采用非标准CMOS工艺.利用铟柱互连混合封装工艺实现SPAD与感应接口电路的协同工作.在低温-30?C的条件下,实现了SPAD光触发雪崩电流信号的提取和快速淬灭.研究了感应电阻和临界检测电压对传感检测电性能的影响,并采用简单电路结构实现状态检测,实测得到的SPAD恢复时间、传输延时分别为575,563 ps,淬灭时间为1.88 ns,满足纳秒级精度传感检测应用的需要. 相似文献
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基于非均匀温度分布效应对互连延时的影响, 提出了一种求解互连非均匀温度分布情况下的缓冲器最优尺寸的模型. 给出了非均匀温度分布情况下的RC互连延时解析表达式, 通过引入温度效应消除因子, 得出了最优插入缓冲器尺寸以使互连总延时最优. 针对90 nm和65 nm工艺节点, 对所提模型进行了仿真验证, 结果显示, 相较于以往同类模型, 本文所提模型由于考虑了互连非均匀温度分布效应, 更加准确有效, 且在保证互连延时最优的情况下有效地提高了芯片面积的利用. 相似文献
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Thermal stability improvement of a multiple finger power SiGe heterojunction bipolar transistor under different power dissipations using non-uniform finger spacing 下载免费PDF全文
A method of non-uniform finger spacing is proposed to enhance thermal stability of a multiple finger power SiGe heterojunction bipolar transistor under different power dissipations. Temperature distribution on the emitter fingers of a multi-finger SiGe heterojunction bipolar transistor is studied using a numerical electro-thermal model. The results show that the SiGe heterojunction bipolar transistor with non-uniform finger spacing has a small temperature difference between fingers compared with a traditional uniform finger spacing heterojunction bipolar transistor at the same power dissipation. What is most important is that the ability to improve temperature non-uniformity is not weakened as power dissipation increases. So the method of non-uniform finger spacing is very effective in enhancing the thermal stability and the power handing capability of power device. Experimental results verify our conclusions. 相似文献
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As feature size keeps scaling down,process variations can dramatically reduce the accuracy in the estimation of interconnect performance.This paper proposes a statistical Elmore delay model for RC interconnect tree in the presence of process variations.The suggested method translates the process variations into parasitic parameter extraction and statistical Elmore delay evaluation.Analytical expressions of mean and standard deviation of interconnect delay can be obtained in a given fluctuation range of interconnect geometric parameters.Experimental results demonstrate that the approach matches well with Monte Carlo simulations.The errors of proposed mean and standard deviation are less than 1% and 7%,respectively.Simulations prove that our model is efficient and accurate. 相似文献
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A simple yet accurate interconnect parasitical capacitance model is presented. Based on this model a novel interconnect bus optimization methodology is proposed. Combining wire spacing with wire ordering, this methodology focuses on bus dynamic power optimization with consideration of bus performance requirements. The optimization methodology is verified under a 65 nm technology node and it shows that with 50% slack in the routing space, a 33.039% power saving can be provided by the proposed optimization methodology for an intermediate video bus compared to the 27.68% power saving provided by uniform spacing technology. The proposed methodology is especially suitable for computer-aided design of nanometer scale on-chip buses. 相似文献
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针对VLSI设计中存在的互连电感效应、热电耦合以及互连温度分布的问题,提出一种缓冲器插入延时优化方法.首先根据互连温度分布的特点得出其电阻模型和延时模型,通过延时、功耗和温度之间的热电耦合效应求得考虑互连温度分布的缓冲器插入最优化延时,利用Matlab软件求得最佳优化结果.采用该方法针对45 nm工艺节点的缓冲器插入进行分析和验证,证实了方法的有效性.研究表明,忽略互连电感效应会高估芯片的优化延时,忽略互连温度分布会低估芯片的优化延时,在全局互连尺寸较小(线宽为245 nm)时,忽略互连温度分布会低估互连延时8.71%. 相似文献