High‐performance In–Zn–O thin‐film transistors with a soluble processed ZrO2 gate insulator

Spin‐coated zirconium oxide films were used as a gate dielectric for low‐voltage, high performance indium zinc oxide (IZO) thin‐film transistors (TFTs). The ZrO₂ films annealed at 400 °C showed a low gate leakage current density of 2 × 10^–8 A/cm² at an electric field of 2 MV/cm. This was attributed to the low impurity content and high crystalline quality. Therefore, the IZO TFTs with a soluble ZrO₂ gate insulator exhibited a high field effect mobility of 23.4 cm²/V s, excellent subthreshold gate swing of 70 mV/decade and a reasonable I_on/off ratio of ～10⁶. These TFTs operated at low voltages (～3.0 V) and showed high drain current drive capability, enabling oxide TFTs with a soluble processed high‐k dielectric for use in backplane electronics for low‐power mobile display applications. (© 2013 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)     

Low-voltage-drive and high output current ZnO thin-film transistors with sputtering SiO2 as gate insulator

Low-voltage-drive ZnO thin-film transistors (TFTs) with room-temperature radio frequency magnetron sputtering SiO₂ as the gate insulator were fabricated successfully on the glass substrate. The ZnO-TFT operates in the enhancement mode with a threshold voltage of 4.2 V, a field effect mobility of 11.2 cm²/V s, an on/off ratio of 3.1 × 10⁶ and a subthreshold swing of 0.61 V/dec. The drain current can reach to 1 mA while the gate voltage is only of 12 V and drain voltage of 8 V. The C–V characteristics of a MOS capacitor with the structure of ITO/SiO₂/ZnO/Al was investigated. The carrier concentration N_D in the ZnO active layer was determined, the calculated N_D is 1.81 × 10¹⁶ cm⁻³, which is the typical value of undoped ZnO film used as the channel layer for ZnO-TFT devices. The experiment results show that SiO₂ film is a promising insulator for the low voltage and high drive capability oxide TFTs.     

SiOx interlayer to enhance the performance of InGaZnO-TFT with AlOx gate insulator

We have fabricated indium–gallium–zinc (IGZO) thin film transistor (TFT) using SiO_x interlayer modified aluminum oxide (AlO_x) film as the gate insulator and investigated their electrical characteristics and bias voltage stress. Compared with IGZO-TFT with AlO_x insulator, IGZO-TFT with AlO_x/SiO_x insulator shows superior performance and better bias stability. The saturation mobility increases from 5.6 cm²/V s to 7.8 cm²/V s, the threshold voltage downshifts from 9.5 V to 3.3 V, and the contact resistance reduces from 132 Ωcm to 91 Ωcm. The performance improvement is attributed to the following reasons: (1) the introduction of SiO_x interlayer improves the insulator surface properties and leads to the high quality IGZO film and low trap density of IGZO/insulator interface. (2) The better interface between the channel and S/D electrodes is favorable to reduce the contact resistance of IGZO-TFT.     

Memory characteristics and tunneling mechanism of Pt nano-crystals embedded in HfAlOx films for nonvolatile flash memory devices

A non-volatile flash memory device based on metal oxide semiconductor (MOS) capacitor structure has been fabricated using platinum nano-crystals(Pt–NCs) as storage units embedded in HfAlO_x high-k tunneling layers. Its memory characteristics and tunneling mechanism are characterized by capacitance–voltage(C–V) and flat-band voltage-time(ΔV_FB-T) measurements. A 6.5 V flat-band voltage (memory window) corresponding to the stored charge density of 2.29 × 10¹³ cm⁻² and about 88% stored electron reserved after apply ±8 V program or erase voltage for 10⁵ s at high frequency of 1 MHz was demonstrated. Investigation of leakage current–voltage(J–V) indicated that defects-enhanced Pool-Frenkel tunneling plays an important role in the tunneling mechanism for the storage charges. Hence, the Pt–NCs and HfAlO_x based MOS structure has a promising application in non-volatile flash memory devices.     

Room temperature fabrication Oxide TFT with Y2O3 as a gate oxide and Mo contact

In this investigation, an operating voltage as low as 5 V has been achieved for Oxide TFT with Y₂O₃ as a gate oxide and a-IGZO as an active layer. The OTFT has been fabricated at room temperature using RF sputter. The mobility and threshold voltages are 11.3 cm²/V s and 3.4 V for the device with W/L = 0.8, respectively. The annealing at 400 °C in N₂ containing 5% H₂ ambient has been utilized to improve the electrical performance of TFT. The on-off current which is determined by gate dielectric has been observed to be 10⁴. It has also been observed that the dielectric properties of gate oxide deteriorate on annealing. The dielectric constant of Y₂O₃ is observed in the range between 5.1 and 5.4 measured on various devices.     

Highly stable hafnium–tin–zinc oxide thin film transistors with stacked bilayer active layers

Hf–Sn–Zn–O (HTZO) thin films were prepared on SiO₂/SiN_x substrates at room temperature by the direct current (DC) magnetron sputtering of Hf-doped Sn–Zn–O targets. The characteristics of films with different amounts of Hf were analyzed. Amorphous HTZO films were obtained by increasing the Hf content, while polycrystalline films have not shown with Hf doping. With the proper Hf concentration in the HTZO films (∼2.0 atomic % Hf/(Hf + Sn + Zn + O)), HTZO films demonstrated good performance as an oxide semiconductor channel material in thin film transistors (TFTs) with a field effect mobility (μ_FE) of 10.9 cm²V⁻¹ s⁻¹, an on/off current ratio of 10⁹, and a subthreshold voltage swing of 0.71 V/decade.     

Surface properties of palladium catalysts supported on ternary ZrO2–Al2O3–WOx oxides prepared by the sol–gel method: Study of the chemical state of the support

The surface properties of Pd and Pd–Pt catalysts supported on binary ZrO₂–WOx and ternary ZrO₂–Al₂O₃–WOx oxides prepared by the sol–gel method were studied. Special attention was paid to the study of the texture of the catalysts as well as the chemical state of tungstated zirconia and tungstated zirconia promoted with alumina in the palladium catalysts. The catalysts were tested in the isomerization of n-hexane and were characterized by N₂ physisorption, XRD, TPR, Raman spectroscopy, XPS and FT-IR of adsorbed pyridine. The catalysts had bimodal pore size distributions with mesopores in the range 55–70 Å and macropores of 1000 Å in diameter. The catalysts had a surface WOx coverage (4.4–6.0 W nm^?2) lower than that of the theoretical monolayer (7.0 W nm^?2). A lower acidity of the ternary ZrO₂–Al₂O₃–WOx oxide as compared to the binary ZrO₂–WOx oxide was found. Higher activity in the isomerisation of n-hexane was obtained in the Pd–Pt catalysts supported on ternary ZrAlW oxides prepared by sol–gel that is correlated with the coexistence on the surface of W⁴⁺ (WO₂) or W⁰ and W⁶⁺ (Al₂(WO₄)₃) species, ZrO₂ in the tetragonal phase and a high amount of ZrOx suboxides species in a low oxidation state (Zr³⁺ and Zr²⁺).     

Thermal stability and dielectric properties of ultrathin CaZrOx films prepared by pulsed laser deposition

The thermal stability and dielectric properties of amorphous CaZrO_x film prepared by pulsed laser deposition (PLD) have been investigated. X-ray diffraction (XRD) investigation shows that CaZrO_x film still remains amorphous after rapid thermal annealing at 700 °C for 10 min. Differential thermal analysis (DTA) indicates that the crystallization temperature of CaZrO_x film is about 729.53 °C, which is significantly higher than that of amorphous ZrO₂ films prepared at the similar conditions. High-resolution transmission electron microscopy (HRTEM) and X-ray photon spectroscopy (XPS) analysis reveal there exists a Si-O transition layer between the CaZrO_x film and Si substrate. The permittivity of CaZrO_x film is about 10.5 (at 1 MHz) by measuring a Pt/CaZrO_x/Pt MIM structure. Under the optimized conditions, a small EOT=0.91 nm and a leakage current density of 125 mA/cm² at 1 V gate voltage were obtained. The enhanced thermal stability and improved electrical characteristics suggest that the amorphous CaZrO_x film may be an attractive gate dielectric alternative for next generation MOS field effect transistor applications. PACS 77.55.+f; 81.15.Fg; 73.40.Qv     

On the step-graded doped-channel (SGDC) field-effect transistor

An i-InGaP/n-In_xGa_1 − xAs/i- GaAs step-graded doped-channel field-effect transistor (SGDCFET) has been fabricated and studied. Due to the existence of a V-shaped energy band formed by the step-graded structure, a large output current density, a large gate voltage swing with high average transconductance, and a high breakdown voltage can be expected. In this study, first, a theoretical model and a transfer matrix technique are employed to analyze the energy states and wavefunctions in the step-graded quantum wells. Experimentally, for a 1  ×  80 μm²gate dimension device, a maximum drain saturation current density of 830 mAmm ^− 1, a maximum transconductance of 188mSmm ^− 1 , a high gate breakdown voltage of 34 V, and a large gate voltage swing 3.3 V with transconductance larger than 150 mSmm ^− 1are achieved. These performances show that the device studied has a good potentiality for high-speed, high-power, and large input signal circuit applications.     

TEOS-based low-pressure chemical vapor deposition for gate oxides in 4H–SiC MOSFETs using nitric oxide post-deposition annealing

The use of SiO₂/4H–SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) can be problematic due to high interface state density (D_it) and low field-effect mobility (μ_fe). Here, we present a tetra-ethyl-ortho-silicate (TEOS)-based low-pressure chemical vapor deposition (LPCVD) method for fabricating the gate oxide of 4H–SiC MOSFETs using nitric oxide post-deposition annealing. SiO₂/4H–SiC MOS capacitors and MOSFETs were fabricated using conventional wet and TEOS oxides. The measured effective oxide charge density (Q_eff) and D_it of the TEOS-based LPCVD SiO₂/4H–SiC MOS capacitor with nitridation were 4.27 × 10¹¹ cm⁻² and 2.99 × 10¹¹ cm⁻²eV⁻¹, respectively. We propose that the oxide breakdown field and barrier height were dependent on the effective Q_eff. The measured μ_fe values of the SiO₂/4H–SiC MOSFETs with wet and TEOS oxides after nitridation were, respectively, 11.0 and 17.8 cm²/V due to the stable nitrided interface between SiO₂ and 4H–SiC. The proposed gate stack is suitable for 4H–SiC power MOSFETs.     

An organic electrophosphorescent device driven by all-organic thin-film transistor using photoacryl as a gate insulator

Organic electrophosphorescent devices have been intensively investigated for using in full-color flat-panel display. Since the quantum efficiency of electrophosphorescent device decreases rapidly as the luminance increases, it is desirable to operate the electrophosphorescent display with active matrix rather than passive matrix. Here we report the study of driving electrophosphorescent diode with all-organic TFT. We obtained the maximum power luminance that was obtained about 90 cd/m². Turn-on voltage is approximately 10 V. Field effect mobility, threshold voltage, and on–off current ratio in 0.5-μm thick gate dielectric layer were 0.13 cm²/V s, −7 V, and 10⁶ A/A. The structure of electrophosphorescent diode is ITO/TPD/BCP:Ir(ppy)₃/BCP/Alq₃/Li:Al/Al. In organic TFT, photoacryl is used as an insulator and pentacene as an active layer.     

氧化锌锡薄膜晶体管的研究

在ITO玻璃基底上用射频磁控溅射技术生长氧化锌锡(ZnSnO)沟道有源层、用PECVD生长SiO₂薄膜作为薄膜晶体管的栅绝缘层研制了薄膜晶体管(TFT), 器件的场效应迁移率最高达到μ_n=9.1 cm²/(V ·s),阈值电压-2 V,电流开关比为10⁴. 关键词： 氧化锌锡 薄膜晶体管 场效应迁移率     

Temperature-dependent current conduction mechanism and charge trapping in Ta2O5 RF-sputtered on GaN

A gallium nitride (GaN) based Metal-Oxide-Semiconductor (MOS) capacitor was fabricated using radio frequency (RF)-sputtered tantalum oxide (Ta₂O₅) as the high-k gate dielectric. Electrical characteristics of this capacitor were evaluated via capacitance–voltage (C–V), current–voltage (I–V), and interface trap density (D_it) measurements with emphasis on the substrate temperature dependence ranging from 25 °C to 200 °C. Charge trapping and conduction mechanism in Ta₂O₅ were investigated. The experimental results suggested that higher substrate temperature rendered higher oxide capacitance, reduced gate leakage current, and lowered mid-gap interface trap density at the expenses of high border traps and high fixed oxide charges. The gate leakage current through Ta₂O₅ was found to obey the Ohm's conduction at lower gate bias and the Poole–Frenkel conduction at higher gate bias.     

Cobalt metal nanoparticles embedded in SiO2 dielectric layer for the application of nonvolatile memory

Metal–oxide–semiconductor structures (MOS) with the embedded Co nanoparticles (NPs) were efficiently fabricated by utilizing an external laser irradiation technique for the application of nonvolatile memory. Images of high resolution transmission electron microscopy measurements exhibited that the Co NPs of 5 nm in diameter were clearly embedded in SiO₂ gate oxide. Capacitance–voltage measurements certainly exhibited flat-band voltage shift of 2.2 V from 2 V to −8 V in sweeping range. The retention characteristics of MOS capacitors with the embedded Co NPs were also studied as a function of tunnel oxide thickness to confirm the suitability of nonvolatile memory devices with metal NPs. The experimental results reveal that our unique laser process will give possible promise for experimental efficient formation or insertion of metal NPs inside the gate oxide.     

Fabricating high performance n-channel lateral double diffused metal–oxide–semiconductor transistors utilizing the shallow trench isolation as a salicide blocking mask of the drift region

In this paper, the improved characteristics of 10 V tolerant high-voltage n-channel lateral double diffused metal–oxide–semiconductor (LDMOS) devices, using a pure 0.25 μm standard low-voltage complementary metal–oxide–semiconductor (CMOS) logic process with dual gate oxide, are described. The fabricated transistors showed about 30% better current driving characteristics and about 40% higher drain operating voltage than previous reports of these kinds of devices. The transistors maintained a breakdown voltage, BV_DSS, over 14 V. These devices also showed good sub-threshold characteristics. This paper describes the cost-effective and high performance n-channel high-voltage LDMOS using a pure low-voltage standard CMOS logic process.     

Structure and dielectric properties of ultra-thin ZrO<Subscript>2</Subscript> films for high-<Emphasis Type="Italic">k</Emphasis> gate dielectric application prepared by pulsed laser deposition

ZrO₂ thin films have been prepared on Pt-coated silicon substrates and directly on n-Si(100) substrates by the pulsed laser deposition (PLD) technique using a ZrO₂ ceramic target under different deposition conditions. X-ray diffraction showed that the films prepared at 400 °C in 20 Pa oxygen ambient remained amorphous. Differential thermal analysis was carried out to study the crystallization behavior of ZrO₂. The dielectric constant of ZrO₂ was determined to be around 24 by measuring a Pt/ZrO₂/Pt capacitor structure. Sputtering depth profile X-ray photoelectron spectroscopy was used to investigate the interfacial characteristics of ZrO₂/n-Si stacks. A Zr silicate interfacial layer was formed between the ZrO₂ layer and the silicon substrate. The equivalent oxide thickness (EOT) and leakage current densities of the films with 6.6 nm physical thickness post-annealed in O₂ and N₂ ambient were investigated. An EOT of 1.65 nm with a leakage current of 36.2 mA/cm² at 1 V gate voltage for the film post-annealed in N₂ has been obtained. ZrO₂ thin films prepared by PLD have acceptable structure and dielectric properties required by a candidate material of high-k gate dielectrics. PACS 77.55.+f; 81.15.Fg; 73.40.Qv     

Improved electrical properties of HfTiO/GeO x N y gate dielectric Ge MOS capacitors by using wet–NO Ge-surface pretreatment

Reactive cosputtering is employed to prepare high-permittivity HfTiO gate dielectric on n-Ge substrate. Effects of Ge-surface pretreatment on the interface and gate leakage properties of the dielectric are investigated. Excellent performances of Al/HfTiO/GeO _x N _y /n-Ge MOS capacitor with wet–NO surface pretreatment have been achieved with a interface-state density of 2.1×10¹¹ eV⁻¹ cm⁻², equivalent oxide charge of −7.67×10¹¹ cm⁻² and gate leakage current density of 4.97×10⁻⁵ A/cm² at V _g =1 V.     

Effect of Y2O3 doping on the electrical transport properties of Sr2MnNiFe12O22 Y-type hexaferrite

Y₂O₃ doped Y-type composite hexa-ferrites Sr₂MnNiFe₁₂O₂₂ + xY₂O₃ (x = 0 wt%, 1 wt%, 2 wt%, 3 wt%, 4 wt%, 5 wt%) were synthesized successfully using sol-gel auto combustion technique. X-ray diffraction analysis reveals Y-type hexagonal structure with few traces of secondary phases. The decrease in grain size as a function of Yttrium content is attributed to the fact that Yttrium acts as a grain inhibitor. The DC resistivity was observed to increase with increasing Yttrium-contents due to the unavailability of Fe³⁺ ions at octahedral sites. Activation energy showed that the samples with high resistivity have high value of activation energy and vice versa. Permittivity decreases with the increase of frequency following Maxwell Wagner Model. In addition, the doped samples exhibit very low dielectric constant and low loss tangent in frequency range 20 Hz–1 MHz. The sample x = 5 wt% exhibit the lowest value of dielectric constant. The variation in imaginary part of dielectric constant and loss tangent with frequency show normal dielectric behavior for all the samples. The frequency dependent ac conductivity increases with increase in frequency and decrease with Y₂O₃ doping. These characteristics may be suitable for their potential applications in electromagnetic attenuation materials and microwave devices. The conductivity mechanism so determined was hopping mechanism. The dc resistivity of the doped ferrites measured in our case is about 10¹⁰ Ω-cm that meets the requirement for fabrication of components by electroplating.     

Dielectric,ferroelectric and field-induced strain response of lead-free BaZrO3-modified Bi0.5Na0.5TiO3 ceramics

Lead-free piezoelectric ceramics (1 − x)Bi_0.5Na_0.5TiO₃–xBaZrO₃ (BNT–BZ100x, with x = 0–0.10) were prepared using a conventional solid-state reaction method. The crystal structure, microstructure, dielectric, ferroelectric, and piezoelectric properties of BNT–BZ100x ceramics were studied as functions of different BZ content. X-ray diffraction patterns revealed that the BZ completely diffused in the BNT lattice in the studied composition range. An appropriate amount of BZ addition improved the dielectric, ferroelectric, and piezoelectric properties of BNT ceramics. The remanent polarization (P_r) and piezoelectric constant (d₃₃) increased from 22 μC/cm² and 60 pC/N for pure BNT to 30 μC/cm² and 112 pC/N for x = 0.040, respectively. In addition, electric field-induced strain was enhanced to its maximum value (S_max = 0.40%) with normalized strain (d*₃₃ = S_max/E_max = 500 pm/V) at an applied electric field of 8 kV/mm for x = 0.055. The enhanced strain can be attributed to the coexistence of ferroelectric and relaxor ferroelectric phases.     

Swift ion irradiation effect on high-k ZrO2- and Al2O3-based MOS devices

This paper describes the heavy ion-induced effects on the electrical characteristics of reactively sputtered ZrO₂ and Al₂O₃ high-k gate oxides deposited in argon plus nitrogen containing plasma. Radiation-induced degradation of sputtered high-k dielectric ZrO₂/Si and Al₂O₃/Si interface was studied using 45?MeV Li³⁺ ions. The devices were irradiated with Li³⁺ ions at various fluences ranging from 5?×?10⁹ to 5?×?10¹²?ions/cm². Capacitance–voltage and current–voltage characteristics were used for electrical characterization. Shift in flat band voltage towards negative value was observed in devices after exposure to ion radiation. Post-deposition annealing effect on the electrical behavior of high-k/Si interface was also investigated. The annealed devices showed better electrical and reliability characteristics. Different device parameters such as flat band voltage, leakage current, interface defect density and oxide-trapped charge have been extracted.The surface morphology and roughness values for films deposited in nitrogen containing plasma before and after ion radiation are extracted from Atomic Force Microscopy.