Development of a prototype of the ME readout electronics onboard the HXMT satellite

A prototype of the ME readout electronics onboard the Hard X-ray Modulate Telescope (HXMT) satellite is developed. Application Specific Integrated Chip (ASIC) is used to construct the front end electronics due to a large number of detectors. Field Programmable Gate Array (FPGA) is connected to the ASIC as a state machine controller and data FIFO in the DAQ system. A USB board is designed to communicate between the DAQ system and the computer. The design goals and features, the operation of the system and the preliminary performance of the prototype are described. The testing results show that the design goals of the prototype system have been achieved.     

Images of triple gas electron multiplier with pixel-pads

Testing of a triple gas electron multiplier (GEM) with pixel-pads is described. Images by scanning and suspending radioactive sources were obtained by using 96 channels digital data acquisition (DAQ) system which was composed of 96 8× 8~mm² pads and associated electronics channels.     

A Simple X-ray Spectrometer and PC-based Data Acquisition System for Newly Developed X-ray Source Based on Laser Compton Scattering

A simple X-ray spectrometer and a PC-Based Data Acquisition System(DAS) have been developed newly in Shanghai Institute of Applied Physics(SINAP),Chinese Academy of Sciences (CAS) for the measurement of the X-ray source generated using laser Compton scattering.The system consists of liquid nitrogen cooled high resolution Si(Li) detector,electronics and a DAQ.The Si(Li) detector was designed and made by Center of Advanced Instruments in SINAP,CAS,it allows us to measure X-rays with the energy up to 60 keV and the energy resolution(FWHM) of 184 eV at 5.9 keV.We measured the system uncertainty was 0.2 eV and time drifting of detector was 0.05% both at 5.9 keV.The DAQ was based on Object-Oriented software LabVIEW 7.1,it has data on-line analysis and original data saved functions.     

A Flash-ADC data acquisition system developed for a drift chamber array and a digital filter algorithm for signal processing

A Flash-ADC data acquisition (DAQ) system has been developed for the drift chamber array designed for the External-Target-Experiment at the Cooling Storage Ring at the Heavy Ion Research Facility, Lanzhou. The simplified readout electronics system has been developed using the Flash-ADC modules and the whole waveform in the sampling window is obtained, with which the time and energy information can be deduced with an offline processing. A digital filter algorithm has been developed to discriminate the noise and the useful signal. With the digital filtering process, the signal to noise ratio (SNR) is increased and a better time and energy resolution can be obtained.     

基于SCA ASIC的高精度时间测量原型电子学设计

基于高速波形数字化实现高精度时间测量是核与粒子物理实验读出电子学中的研究热点。本工作针对高精度时间测量的需求基于实验室自主研发的开关电容阵列(Switched Capacitor Array, SCA)专用集成电路(Application Specific Integrated Circuit,ASIC)开展16通道集成的时间测量电子学原型的设计,输入信号经过SCA采样和量化后传输至现场可编程逻辑阵列(Field Programmable Gate Array, FPGA),在FPGA中进行误差修正、时间内插和数字甄别提取出时间信息。目前已在实验室环境下完成此电子学的时间精度测试,测试结果表明,此电子学可以实现好于10 ps RMS(Root Mean Square)的时间精度。     

A prototype silicon detector system for space cosmic-ray charge measurement

A readout electronics system used for space cosmic-ray charge measurement for multi-channel silicon detectors is introduced in this paper, including performance measurements. A 64-channel charge sensitive ASIC (VA140) from the IDEAS company is used. With its features of low power consumption, low noise, large dynamic range, and high integration, it can be used in future particle detecting experiments based on silicon detectors.     

基于PC-Linux的STAR TOFp探测器的数据获取系统

廉价的运行开放源代码操作系统Linux的硬件在高能物理领域中正扮演着各种各样重要的角色.本文描述了为STARTOFp探测器设计的基于PC-Linux的数据获取系统.系统采用了常规的解决方案:由一台运行Linux的PC来控制由NIM和CAMAC插件构成的前端电子学处理部分.系统已经被成功的集成进STAR数据获取系统,并且在STAR的第二年的运行中工作正常.     

基于FPGA的储存环束流轨道联锁系统设计

上海光源储存环束流轨道联锁系统是加速器机器联锁保护系统(MPS)的重要组成部分,针对日常供光和机器研究的需求,需要对束流位置测量系统前各Libera电子学输出的联锁信号进行标记,以区分联锁信号的先后顺序和误报的联锁信号,同时触发所有Libera电子学前锁存逐圈(TBT)数据。新的联锁系统将所有联锁信号通过光纤传输汇总至FPGA数据采集板卡进行甄别,并将该系统集成储存环EPICS控制系统中。实验室测试显示该系统能够能够分辨数十ns范围内模拟的联锁信号,同时输出特定的触发信号至对应的Libera电子学,表明该系统达到设计要求。     

2维位置灵敏中子探测器读出

 介绍了基于厚型气体电子倍增探测器(THGEM)的位置灵敏热中子探测器中,采用专用集成电路的阵列电荷灵敏前置放大和可编程器件的读出电子学设计。专用集成电路采用VA64TA2,64通道输入电荷灵敏放大成型,触发输出。控制电路使用了现场可编程器件。两者结合,显著减少了读出电路在探测器内所占据的空间。介绍了VA64TA2裸片的封装,给出了电路的原理和时序,进行了线性和电子学噪声试验,结果表明电路具有16 fC的线性动态范围,电子学噪声仅为75个电子电荷。     

HIRFL-CSR外靶实验T0探测器前端电子学原型模块设计

介绍了兰州重离子加速器冷却储存环（HIRFL-CSR）外靶实验中时间起点探测器（T0）的前端电子学原型模块的设计与测试。探索了基于过阈时间法和专用集成电路NINO芯片进行多气隙电阻板室探测器信号读出的模拟前端电路的设计技术,并实际完成了原型电子学模块的设计。此模块共集成6个测量通道,可以进行前沿甄别及电荷时间变换。目前已经在实验室条件下完成了各项电子学性能测试,包括不同甄别阈值下的时间精度测试以及不同输入信号幅度下的输出脉宽测试。测试结果表明,在100 fC至2 pC的动态范围内,此模块时间精度好于20 ps,满足应用需求,这也为进一步的电子学系统设计做好了准备。A prototype front end electronics (FEE) module is designed for the T0 detector in the External Experiment in CSR (Cooling Storage Ring) of HIRFL (Heavy Ion Research Facility in Lanzhou). Based on the Time-Over-Threshold method and NINO ASIC, a total of 6 channels are integrated in the module, and both high precision leading edge discrimination and Charge-to-Time Conversion can be achieved, which satisfies the readout requirement of MRPC (Multi-gap Resistive Plate Chamber). A series of tests were also conducted in the laboratory, including time precision tests with different thresholds and output pulse width tests with different input signal amplitudes. Test results indicate that this prototype module functions well, and the time precision is better than 20 ps in the dynamic range from 100 fC to 2 pC, which is beyond application requirement. Through this work, preparation is made for the future readout system design.     

12 bit 30 MSPS逐次比较型ADC的测试

针对物理实验读出的需求设计了一款低功耗12 bit 30 MSPS逐次比较型模数变换器（Analog-to-Digital Converter,ADC）芯片,为评估其性能指标参数,需进行系统的测试。在本研究工作中构建了测试系统,然后按照IEEE标准进行了系统的测试和分析。测试结果表明,输入信号在基带范围内ADC有效位（Effective Number Of Bit,ENOB）约为9 bit,达到了本版本芯片的设计指标。同时,综合分析静态性能与动态性能测试结果,可以通过优化逐次比较型ADC中电容阵列电容失配参数,进一步提升ADC的非线性指标,为下一版芯片的改进设计提供了参考依据。Aiming at the requirement of readout electronics in physics experiments, a 12 bit 30 MSPS successiveapproximation-register (SAR) analog-to-digital converter (ADC) with low power consumption has been designed. To evaluate the performance of this ASIC, we conducted a series of tests. We set up a test system, and we tested the ADC according to IEEE std 1241-2010. The test results indicate that the effective number of bit (ENOB) of the ADC is around 9 bits when the input signal is in the first Nyquist zone, which has met the design requirements. According to the results of dynamic and static tests of this ADC, we found that the non-linearity performance of this ASIC can be further enhanced by improving the mismatching among the capacitor array, and this provides important information for the design of the second version of this ADC.     

塑料闪烁体阵列探测器读出ASIC中峰值保持电路的设计

塑料闪烁体阵列探测器(PSD,简称塑闪阵列探测器)的输出信号经过前置放大器和滤波成形电路后输出准高斯波形,利用峰值保持电路可对准高斯波形信号的峰值进行采样和保持,以便后续的电子学系统对其进行进一步的分析。本工作采用180 nm CMOS工艺设计并实现了一款峰值保持电路ASIC芯片,每通道主要由跨导放大器(OTA)、电流镜和充电电容三部分电路组成。实验室电子学功能和性能测试结果表明:峰值保持电路功能良好;输入动态范围为33~940 mV,非线性误差优于0.8%,下垂速率好于8.6 μV/μs,峰值探测延迟时间小于35 ns,芯片单通道静态功耗为825 μW,达到设计要求。     

LHAASO WCDA前端芯片批量测试系统的设计

LHAASO(Large High Altitude Air Shower Observatory)WCDA(Water Cerenkov Detector Array)要求其读出电子学实现大动态范围下精确的时间和电荷测量，为此设计了一款前端读出芯片PASC(Pre-Amplifier and Shaping Circuit) ASIC(Application Specific Integrated Circuit)，即将用于LHAASO WCDA第三水池的读出。为了满足对此芯片大批量测试需求，设计了此ASIC测试系统，实现了对芯片时间和电荷性能的自动化测试。在介绍此芯片基本工作原理的基础上，讨论了测试系统的设计方案和基本结构，包括硬件电路设计和自动化测试软件设计。该测试系统已应用于LHAASO工程项目的芯片筛选并且已完成了100片芯片的测试工作，能够通过中央控制软件，与多台仪器通讯，进行仪器控制，完成自动化测试和数据记录。这一自动化测试方法，更适用于大动态范围下、高精度读出芯片的性能测试和评估，大大简化测试流程，尤其能够大幅提升批量测试中大量重复性测试步骤的工作效率。文中展示了基于此测试系统已完成的100片芯片的测试结果，结果表明，芯片各项性能参数满足LHAASO第三水池工程应用需求。     

Status of the front-end-electronics for the time-of-flight measurements at the MPD experiment

The preamplifier based on the ASIC NINO for the Time of Flight system (TOF) of MPD/NICA was developed and tested. The signal is read from both sides of the strip of the multi gap Resistive Plate Chamber (MRPC). In total there are around 14000 channels of electronics. To measure time of flight of secondary particles from collision of heavy ions on the collider NICA the Time over Threshold (ToT) method is used. According to the bench tests the preamplifier board showed stable work and good time resolution <10 ps for one channel. It was also tested at the test beam facility of the Nuclotron. The time resolution of the TOF detector which used the described preamplifier was reached ～42 ps.     

Very forward calorimeters readout and machine interface

The paper describes the requirements for the readout electronics and DAQ for the instrumentation of the forward region of the future detector at the international linear collider. The preliminary design is discussed. on behalf of the FCAL Collaboration     

Prototype of time digitizing system for BESⅢ endcap TOF upgrade

The prototype of a time digitizing system for the BESⅢ endcap TOF (ETOF) upgrade is introduced in this paper. The ETOF readout electronics has a distributed architecture. Hit signals from the multi-gap resistive plate chamber (MRPC) are signaled as LVDS by front-end electronics (FEE) and are then sent to the back-end time digitizing system via long shield differential twisted pair cables. The ETOF digitizing system consists of two VME crates, each of which contains modules for time digitization, clock, trigger, fast control, etc. The time digitizing module (TDIG) of this prototype can support up to 72 electrical channels for hit information measurement. The fast control (FCTL) module can operate in barrel or endcap mode. The barrel FCTL fans out fast control signals from the trigger system to the endcap FCTLs, merges data from the endcaps and then transfers to the trigger system. Without modifying the barrel TOF (BTOF) structure, this time digitizing architecture benefits from improved ETOF performance without degrading the BTOF performance. Lab experiments show that the time resolution of this digitizing system can be lower than 20 ps, and the data throughput to the DAQ can be about 92 Mbps. Beam experiments show that the total time resolution can be lower than 45 ps.     

Prototype of time digitizing system for BESⅢ endcap TOF upgrade

The prototype of a time digitizing system for the BESⅢ endcap TOF (ETOF) upgrade is introduced in this paper. The ETOF readout electronics has a distributed architecture. Hit signals from the multi-gap resistive plate chamber (MRPC) are signaled as LVDS by front-end electronics (FEE) and are then sent to the back-end time digitizing system via long shield differential twisted pair cables. The ETOF digitizing system consists of two VME crates, each of which contains modules for time digitization, clock, trigger, fast control, etc. The time digitizing module (TDIG) of this prototype can support up to 72 electrical channels for hit information measurement. The fast control (FCTL) module can operate in barrel or endcap mode. The barrel FCTL fans out fast control signals from the trigger system to the endcap FCTLs, merges data from the endcaps and then transfers to the trigger system. Without modifying the barrel TOF (BTOF) structure, this time digitizing architecture benefits from improved ETOF performance without degrading the BTOF performance. Lab experiments show that the time resolution of this digitizing system can be lower than 20 ps, and the data throughput to the DAQ can be about 92 Mbps. Beam experiments show that the total time resolution can be lower than 45 ps.     

Interface design in nanosystems of Advanced Superionic Conductors

First attempt of practical realization of new interface engineering approach “from advanced materials to advanced devices” for nanosystems of Advanced Superionic Conductors (ASICs), based on AgI (CuI) compounds is presented. Crystallochemical method of symmetry perfect ASIC//electrode interface searching is developed. Some new theoretical results of ASIC//indifferent electrode conjugated commensurate heteropairs with coherent interfaces and preliminary experimental results of the creation of thin-film supercapacitor — prototype based on the lattice matched heterojunction — are given. Future perspectives of the ASIC//electrode interface design suited for micro(nano)electronics and microsystem technology (MST) are discussed. Paper presented at the Patras Conference on Solid State Ionics — Transport Properties, Patras, Greece, Sept. 14–18, 2004.     

A prototype scalable readout system for micro-pattern gas detectors

A scalable readout system(SRS) is designed to provide a general solution for different micro-pattern gas detectors in various applications.The system mainly consists of three kinds of modules:the ASIC card,the adapter card and the front-end card(FEC).The ASIC cards,mounted with particular ASIC chips,are designed for receiving detector signals.The adapter card is in charge of digitizing the output signals from several ASIC cards.The PEC,edged-mounted with the adapter,has field-programmable gate array(FPGA)-based reconfigurable logic and I/O interfaces,allowing users to choose different ASIC cards and adapters for different experiments,which expands the system to various applications.The FEC transfers data through Gigabit Ethernet protocol realized by a TCP processor(SiTCP) IP core in FPGA.By assembling a flexible number of FECs in parallel through Gigabit Ethernet,the readout system can be tailored to specific sizes to adapt to the experiment scales and readout requirements.In this paper,two kinds of multi-channel ASIC chip,VA140 and AGET,are applied to verify the scalability of this SRS architecture.Based on this VA140 or AGET SRS,one FEC covers 8 ASIC(VA140) cards handling 512 detector channels,or 4 ASIC(AGET) cards handling 256 detector channels,respectively.More FECs can be assembled in crates to handle thousands of detector channels.     

A data transmission method for particle physics experiments based on Ethernet physical layer

Due to its advantages of universality, flexibility and high performance, fast Ethernet is widely used in readout system design for modern particle physics experiments. However, Ethernet is usually used together with the TCP/IP protocol stack, which makes it difficult to implement readout systems because designers have to use the operating system to process this protocol. Furthermore, TCP/IP degrades the transmission efficiency and real-time performance. To maximize the performance of Ethernet in physics experiment applications, a data readout method based on the physical layer(PHY) is proposed. In this method, TCP/IP is replaced with a customized and simple protocol, which makes it easier to implement. On each readout module, data from the front-end electronics is first fed into an FPGA for protocol processing and then sent out to a PHY chip controlled by this FPGA for transmission.This kind of data path is fully implemented by hardware. From the side of the data acquisition system(DAQ),however, the absence of a standard protocol causes problems for the network related applications. To solve this problem, in the operating system kernel space, data received by the network interface card is redirected from the traditional flow to a specified memory space by a customized program. This memory space can easily be accessed by applications in user space. For the purpose of verification, a prototype system has been designed and implemented.Preliminary test results show that this method can meet the requirements of data transmission from the readout module to the DAQ with an efficient and simple manner.