A novel circuit design for complementary resistive switch-based stateful logic operations

Recently, it has been demonstrated that memristors can be utilized as logic operations and memory elements. In this paper, we present a novel circuit design for complementary resistive switch(CRS)-based stateful logic operations. The proposed circuit can automatically write the destructive CRS cells back to the original states. In addition, the circuit can be used in massive passive crossbar arrays which can reduce sneak path current greatly. Moreover, the steps for CRS logic operations using our proposed circuit are reduced compared with previous circuit designs. We validate the effectiveness of our scheme through Hspice simulations on the logic circuits.     

基于逻辑门限值的客车ABS硬件在环测试研究

针对ABS控制器开发过程中纯数值仿真过于理想化,实车试验成本高、周期长等缺点,设计并搭建了客车ABS硬件在环仿真测试系统;系统由xPC目标实时仿真环境、气制动系统及整车动力学模型组成;气制动系统按照真实客车制动系统并配合力传感器搭建;整车动力学模型由轮胎模型、七自由度车辆模型、制动器模型等组成,并利用Simulink建模;在ABS控制策略中引入逻辑门限值控制,在客车ABS硬件在环仿真测试系统上测试了客车在高附着系数、低附着系数及对接路面上的制动情况;试验表明:逻辑门限值控制能很好地将车轮滑移率控制在最佳滑移率附近,具有较好的控制精度及鲁棒性。