Development of a multi-channel readout ASIC for a fast neutron spectrometer based on GEM-TPC

A multi-channel front-end ASIC has been developed for a fast neutron spectrometer based on Gas Electron Multiplier(GEM)-Time Projection Chamber(TPC). Charge Amplifier and Shaping Amplifier for GEM(CASAGEM) integrates 16+1 channels: 16 channels for anodes and 1 channel for cathode. The gain and the shaping time are adjustable from 2 to 40 mV/fC and from 20 to 80 ns, respectively. The prototype ASIC is fabricated in0.35 μm CMOS process. An evaluation Print Circuit Board(PCB) was also developed for chip tests. In total 20 chips have been tested. The integrated nonlinearity is less than 1%. The equivalent noise electrons is less than 2000 e when the input capacitor is 50 pF. The time jitter is less than 1 ns. The design and the test results are presented in the paper.     

利用随机拓扑方法分析系统级高功率微波效应

为研究高功率微波与复杂系统的耦合问题,提出了随机拓扑方法。该方法是一种新的系统级电磁敏感度分析预测方法,它结合电磁拓扑理论和随机耦合模型理论,可对包含多个腔体的复杂系统的短波电磁耦合问题进行统计分析。介绍了随机拓扑方法的理论基础,并利用计算机机箱搭建了双腔体和多腔体实验平台。使用该方法对目标位置处感应电压的统计分布进行了预测,并与其他方法得到的感应电压分布进行了比较,其结果基本一致,从而证明了该方法的可行性和准确性。     

辐射源旋转台阶成像技术

 提出了用旋转台阶对辐射源成像的方法。对台阶响应曲线微分可得到辐射源2维出射强度沿台阶方向的1个投影，通过旋转台阶体，可得到完整的正弦图，从而可用层析重建算法重建出辐射源区的强度分布。用钨合金台阶体在1个60Co源上进行成像实验，从400个角度的台阶响应数据重建出60Co源活性区图像，表明该方法是可行的。此方法可推广到大孔径圆孔台阶体，用于测量X射线焦点等小尺寸辐射源的尺寸。     

中子照相CCD成像系统反射镜引入本底分析

 在基于CCD相机的中子照相系统中,反射镜距离闪烁屏太近就会将部分荧光反射回闪烁屏,将闪烁屏照亮,入射中子束的少部分还会被反向散射回闪烁屏,形成图像本底叠加在图像上,对定量分析和CT重建结果产生影响。为此建立了反射镜所引入反射分量的计算方法,可根据闪烁屏受照分布和反射镜参数计算反射分量的分布,并对中子反向散射进行了蒙特卡罗模拟,计算结果与实验测量的本底分布规律相符。     

Development of a multi-channel readout ASIC for a fast neutron spectrometer based on GEM-TPC

A multi-channel front-end ASIC has been developed for a fast neutron spectrometer based on Gas Electron Multiplier （GEM）-Time Projection Chamber （TPC）. Charge Amplifier and Shaping Amplifier for GEM （CASAGEM） integrates 16＋1 channels： 16 channels for anodes and 1 channel for cathode. The gain and the shaping time are adjustable from 2 to 40 mV/fC and from 20 to 80 ns, respectively. The prototype ASIC is fabricated in 0.35 μm CMOS process. An evaluation Print Circuit Board （PCB） was also developed for chip tests. In total 20 chips have been tested. The integrated nonlinearity is less than 1%. The equivalent noise electrons is less than 2000e when the input capacitor is 50 pF. The time jitter is less than 1 ns. The design and the test results are presented in the paper.     

外场激励下腔内屏蔽电缆响应的方法研究

 将时域有限差分（FDTD）法和外场激励下屏蔽电缆的传输线模型相结合,研究计算了外场激励下带缝金属腔内屏蔽电缆的终端负载响应。首先利用FDTD计算了腔内屏蔽电缆处的激励场,然后由得到的激励场和外场激励下屏蔽电缆的传输线模型计算得到屏蔽电缆的终端响应。研究表明,屏蔽电缆对外场干扰具有良好的屏蔽性能。该方法需要的内存和计算量较小,并且使用简单方便。