MoSi2-SiC复合材料制备及抗热震性能研究

本文采用直接熔渗法制备二硅化钼-碳化硅(MoSi2-SiC)复合材料.以碳化硅(SiC)(粒度为0～2.5 mm、≤240目)为主要原料,水溶性树脂为结合剂,经混炼、成型、烘干后得到SiC坯体,再用二硅化钼(MoSi2)(D50 =3μm)粉末掩埋SiC坯体,在真空条件下2000℃保温3h进行熔渗烧结,制备出MoSi2-SiC复合材料.采用阿基米德排水法研究了MoSi2-SiC复合材料的显气孔率、体积密度;采用三点抗弯法测试了MoSi2-SiC复合材料1400℃抗折强度;采用热线法测试了MoSi2-SiC复合材料导热系数;采用X射线衍射测试了MoSi2-SiC复合材料的物相组成;采用SEM测试了MoSi2-SiC复合材料的显微结构;分别采用风冷法和水冷法对比研究了MoSi2-SiC复合材料、重结晶碳化硅(R-SiC)、氮化硅-碳化硅(Si3N4-SiC)三种材料抗热震性.结果表明:MoSi2在烧结过程中部分发生分解,生成了Mo5Si3,MoSi2、Mo5Si3填充于SiC的内部并实现烧结致密化,使MoSi2-SiC复合材料的显气孔率显著降低至5.7;,体积密度为3.59 g.cm-3.MoSi2-SiC复合材料中MoSi2、Mo5Si3含量分别为10wt; ～ 15wt;、3wt; ～ 5wt;.1000℃下MoSi2-SiC的导热系数为46.5W·m-1 ·K-1,显著高于R-SiC(28.3 W.m-1.K-1)材料、Si3N4-SiC(16.8 W.m-1.K-1)材料.综上所述,MoSi2-SiC复合材料的抗热震性能显著优于R-SiC材料、Si3N4-SiC材料.     

Insight into influence of thermodynamic coefficients on transient negative capacitance in Zr-doped HfO2 ferroelectric capacitors

We study the influence of the thermodynamic coefficients on transient negative capacitance for the Zr-doped HfO₂ (HZO) ferroelectric capacitors by the theoretical simulation based on the Landau-Khalatnikov (L-K) theory and experimental measurement of electrical properties in the resistor-ferroelectric capacitor (R-FEC) circuit. Our results show that the thermodynamic coefficients α, β and γ also play a key role for the transient NC effect besides the viscosity coefficient and series resistor. Moreover, the smaller coefficients α and β, the more significant the transient NC effect. In addition, we also find that the thermodynamic process of transient NC does not obey the generally accepted viewpoint of Gibbs free energy minimization.     

Angle-resolved x-ray photoelectron spectroscopy study of GeO_x growth by plasma post-oxidation

The growth process of GeO_x films formed by plasma post-oxidation(PPO) at room temperature(RT) is investigated using angle-resolved x-ray photoelectron spectroscopy(AR-XPS). The experimental results show that the distributions of the Ge~(4+)states, a mixture of the Ge_(2+)and Ge~(3+)states, and the Ge~(1+)states are localized from the GeO_x surface to the GeO_x/Ge interface. Moreover, the Ge~(1+)states are predominant when the two outermost layers of Ge atoms are oxidized.These findings are helpful for establishing in-depth knowledge of the growth mechanism of the GeO_x layer and valuable for the optimization of Ge-based gate stacks for future complementary metal–oxide–semiconductor(MOS) field-effect transistor(CMOSFET) devices.     

Stress-induced leakage current characteristics of PMOS fabricated by a new multi-deposition multi-annealing technique with full gate last process

In the process of high-k films fabrication, a novel multi deposition multi annealing(MDMA) technique is introduced to replace simple post deposition annealing. The leakage current decreases with the increase of the post deposition annealing(PDA) times. The equivalent oxide thickness(EOT) decreases when the annealing time(s) change from 1 to 2. Furthermore,the characteristics of SILC(stress-induced leakage current) for an ultra-thin SiO_2/HfO_2 gate dielectric stack are studied systematically. The increase of the PDA time(s) from 1 to 2 can decrease the defect and defect generation rate in the HK layer. However, increasing the PDA times to 4 and 7 may introduce too much oxygen, therefore the type of oxygen vacancy changes.     

Effects of charge and dipole on flatband voltage in an MOS device with a Gd-doped HfO_2 dielectric

Gd-doped HfO2 has drawn worldwide interest for its interesting features.It is considered to be a suitable material for N-type metal-oxide-semiconductor(MOS)devices due to a negative flatband voltage(Vfb)shift caused by the Gd doping.In this work,an anomalous positive shift was observed when Gd was doped into HfO2.The cause for such a phenomenon was systematically investigated by distinguishing the effects of different factors,such as Fermi level pinning(FLP),a dipole at the dielectric/SiO2interface,fixed interfacial charge,and bulk charge,on Vfb.It was found that the FLP and interfacial dipole could make Vfbnegatively shifted,which is in agreement with the conventional dipole theory.The increase in interfacial fixed charge resulting from Gd doping plays a major role in positive Vfbshift.     

离子束合成钇硅化物的结构及红外谱特征

将稀土金属钇离子注入到n型单晶Si(111)中制备出钇硅化物埋层.利用x射线衍射、卢瑟福背散射和傅里叶红外吸收谱测量分析了样品的结构、原子的埋层分布和振动模式.结果表明，Y离子在注入过程中已与基底中的Si原子形成了YSi2结构相.真空下的红外光辐照处理促使YSi2择优取向生长，埋层中Si与Y的平均原子浓度比由24下降为20，与六方YSi2的化学计量比一致.还给出了钇硅化物的特征红外吸收谱.     

Analysis of flatband voltage shift of metal/high-k/SiO2/Si stack based on energy band alignment of entire gate stack

A theoretical model of flatband voltage(VFB) of metal/high-k/SiO2/Si stack is proposed based on band alignment of entire gate stack, i.e., the VFBis obtained by simultaneously considering band alignments of metal/high-k, high-k/SiO2 and SiO2/Si interfaces, and their interactions. Then the VFBof TiN/HfO2/SiO2/Si stack is experimentally obtained and theoretically investigated by this model. The theoretical calculations are in good agreement with the experimental results.Furthermore, both positive VFBshift of TiN/HfO2/SiO2/Si stack and Fermi level pinning are successfully interpreted and attributed to the dielectric contact induced gap states at TiN/HfO2 and HfO2/SiO2 interfaces.     

P型Cd1-xZnxTe薄膜的制备及性质研究

采用Cu对共蒸发法制备的Cd1-xZnxTe薄膜进行p型掺杂。用X射线荧光、X射线衍射、扫描电镜、紫外-可见分光光度计、热探针、四探针和台阶仪研究了不同Cu掺杂浓度下Cd1-xZnxTe薄膜退火前后的组分、结构、形貌、光学性质及电学性质的变化。结果表明掺Cu 10%的薄膜在退火后导电类型由P型转变为N型、电阻率增大了几个数量级;掺铜20%的样品退火后导电类型和电阻率未发生明显改变,退火后薄膜表面较为均匀完整;掺铜30%的薄膜透过率显著下降到10%以下,退火前后均为P型薄膜。     

Study on influences of TiN capping layer on time-dependent dielectric breakdown characteristic of ultra-thin EOT high-k metal gate NMOSFET with kMC TDDB simulations

The thickness effect of the TiN capping layer on the time dependent dielectric breakdown(TDDB) characteristic of ultra-thin EOT high-k metal gate NMOSFET is investigated in this paper.Based on experimental results,it is found that the device with a thicker TiN layer has a more promising reliability characteristic than that with a thinner TiN layer.From the charge pumping measurement and secondary ion mass spectroscopy(SIMS) analysis,it is indicated that the sample with the thicker TiN layer introduces more Cl passivation at the IL/Si interface and exhibits a lower interface trap density.In addition,the influences of interface and bulk trap density ratio N_(it)/N_(ot) are studied by TDDB simulations through combining percolation theory and the kinetic Monte Carlo(kMC) method.The lifetime reduction and Weibull slope lowering are explained by interface trap effects for TiN capping layers with different thicknesses.     

Temperature- and voltage-dependent trap generation model in high-k metal gate MOS device with percolation simulation

High-k metal gate stacks are being used to suppress the gate leakage due to tunneling for sub-45 nm technology nodes.The reliability of thin dielectric films becomes a limitation to device manufacturing,especially to the breakdown characteristic.In this work,a breakdown simulator based on a percolation model and the kinetic Monte Carlo method is set up,and the intrinsic relation between time to breakdown and trap generation rate R is studied by TDDB simulation.It is found that all degradation factors,such as trap generation rate time exponent m,Weibull slope β and percolation factor s,each could be expressed as a function of trap density time exponent α.Based on the percolation relation and power law lifetime projection,a temperature related trap generation model is proposed.The validity of this model is confirmed by comparing with experiment results.For other device and material conditions,the percolation relation provides a new way to study the relationship between trap generation and lifetime projection.