Field plate structural optimization for enhancing the power gain of GaN-based HEMTs

A novel source-connected field plate structure, featuring the same photolithography mask as the gate electrode, is proposed as an improvement over the conventional field plate (FP) techniques to enhance the frequency performance in GaN-based HEMTs. The influences of the field plate on frequency and breakdown performance are investigated simultaneously by using a two-dimensional physics-based simulation. Compared with the conventional T-gate structures with a field plate length of 1.2 μm, this field plate structure can induce the small signal power gain at 10 GHz to increase by 5-9.5 dB, which depends on the distance between source FP and dramatically shortened gate FP. This technique minimizes the parasitic capacitances, especially the gate-to-drain capacitance, showing a substantial potential for millimeter-wave, high power applications.     

Model of hot-carrier induced degradation in ultra-deep sub-micrometer nMOSFET

The degradation produced by hot carrier(HC) in ultra-deep sub-micron n-channel metal oxide semiconductor field effect transistor(nMOSFET) has been analyzed in this paper. The generation of negatively charged interface states is the predominant mechanism for the ultra-deep sub-micron nMOSFET. According to our lifetime model of p-channel MOFET(pMOFET) that was reported in a previous publication, a lifetime prediction model for nMOSFET is presented and the parameters in the model are extracted. For the first time, the lifetime models of nMOFET and pMOSFET are unified. In addition, the model can precisely predict the lifetime of the ultra-deep sub-micron nMOSFET and pMOSFET.     

Hot carrier degradation and a new lifetime prediction model in ultra-deep sub-micron pMOSFET

The hot carrier effect (HCE) of an ultra-deep sub-micron p-channel metal-oxide semiconductor field-effect transistor (pMOSFET) is investigated in this paper. Experiments indicate that the generation of positively charged interface states is the predominant mechanism in the case of the ultra-deep sub-micron pMOSFET. The relation of the pMOSFET hot carrier degradation to stress time (t), channel width (W ), channel length (L), and stress voltage (Vd ) is then discussed. Based on the relation, a lifetime prediction model is proposed, which can predict the lifetime of the ultra-deep sub-micron pMOSFET accurately and reflect the influence of the factors on hot carrier degradation directly.     

Effects of stress conditions on the generation of negative bias temperature instability-associated interface traps

The exponent n of the generation of an interface trap(Nit),which contributes to the power-law negative bias temperature instability(NBTI)degradation,and the exponent’s time evolution are investigated by simulations with varying the stress voltage Vgand temperature T.It is found that the exponent n in the diffusion-limited phase of the degradation process is irrelevant to both Vgand T.The time evolution of the exponent n is affected by the stress conditions,which is reflected in the shift of the onset of the diffusion-limited phase.According to the diffusion profiles,the generation of the atomic hydrogen species,which is equal to the buildup of Nit,is strongly correlated with the stress conditions,whereas the diffusion of the hydrogen species shows Vg-unaffected but T-affected relations through the normalized results.     

Resistive switching characteristics of Ti/ZrO2/Pt RRAM device

In this paper, the bipolar resistive switching characteristic is reported in Ti/ZrO2/Pt resistive switching memory devices. The dominant mechanism of resistive switching is the formation and rupture of the conductive filament composed of oxygen vacancies. The conduction mechanisms for low and high resistance states are dominated by the ohmic conduction and the trap-controlled space charge limited current(SCLC) mechanism, respectively. The effect of a set compliance current on the switching parameters is also studied: the low resistance and reset current are linearly dependent on the set compliance current in the log–log scale coordinate; and the set and reset voltage increase slightly with the increase of the set compliance current. A series circuit model is proposed to explain the effect of the set compliance current on the resistive switching behaviors.