Total Dose Radiation Tolerance of Phase Change Memory Cell with GeSbTe Alloy

Phase change memory （PCM） cell array is fabricated by a standard complementary metal-oxide-semiconductor process and the subsequent special fabrication technique. A chalcogenide Ge2Sb2Te5 film in thickness 50hm deposited by rf magnetron sputtering is used as storage medium for the PCM cell. Large snap-back effect is observed in current-voltage characteristics, indicating the phase transition from an amorphous state （higher resistance state） to the crystalline state （lower resistance state）. The resistance of amorphous state is two orders of magnitude larger than that of the crystalline state from the resistance measurement, and the threshold current needed for phase transition of our fabricated PCM cell array is very low （only several μA）. An x-ray total dose radiation test is carried out on the PCM cell array and the results show that this kind of PCM cell has excellent total dose radiation tolerance with total dose up to 2 ×10^6 rad（Si）, which makes it attractive for space-based applications.     

Chemical mechanical planarization of Ge_2Sb_2Te_5 using IC1010 and Politex reg pads in acidic slurry

In the paper, chemical mechanical planarization(CMP) of Ge2Sb2Te5(GST) is investigated using IC1010 and Politex reg pads in acidic slurry. For the CMP with blank wafer, it is found that the removal rate(RR) of GST increases with the increase of pressure for both pads, but the RR of GST polished using IC1010 is far more than that of Politex reg. To check the surface defects, GST film is observed with an optical microscope(OM) and scanning electron microscope(SEM). For the CMP with Politex reg, many spots are observed on the surface of the blank wafer with OM, but no obvious spots are observed with SEM. With regard to the patterned wafer, a few stains are observed on the GST cell, but many residues are found on other area with OM. However, from SEM results, a few residues are observed on the GST cell, more dielectric loss is revealed about the trench structure. For the CMP with IC1010, the surface of the polished blank wafer suffers serious scratches found with both OM and SEM, which may result from a low hardness of GST, compared with those of IC1010 and abrasives. With regard to the patterned wafer, it can achieve a clean surface and almost no scratches are observed with OM, which may result from the high-hardness SiO2 film on the surface, not from the soft GST film across the whole wafer. From the SEM results, a clean interface and no residues are observed on the GST surface, and less dielectric loss is revealed. Compared with Politex reg, the patterned wafer can achieve a good performance after CMP using IC1010.     

Ge2Sb2Te5的化学机械抛光研究进展

相变存储器由于具有非易失性、高速度、低功耗等优点被认为最有可能成为下一代存储器的主流产品,Ge2Sb2Te5(GST)作为一种传统相变材料已经被广泛应用在相变存储器中,而GST的化学机械抛光作为相变存储器生产的关键工艺目前已被采用.本工作综述了有关GST的化学机械抛光技术研究进展,讨论了GST化学机械抛光过程的影响因素,如下压力、转速、抛光垫、磨料、氧化剂、表面活性剂等,并对目前GST的化学机械抛光机理进行了归纳,进一步展望了GST的化学机械抛光技术的发展前景.     

Thermal effect of Ge_2Sb_2Te_5 in phase change memory device

The properties of Raman phonons are very important due to the fact that they can availably reflect some important physical information. An abnormal Raman peak is observed at about 558 cm-1in In film composed of In/InOx core–shell structured nanoparticles, and the phonon mode stays very stable when the temperature changes. Our results indicate that this Raman scattering is attributed to the existence of incomplete indium oxide in the oxide shell.     

Enhanced Performance of Phase Change Memory Cell Element by Initial Operation and Non-Cumulative Programming

A phase change memory （PCM） device, based on the Ge2Sb2Te5 （GST） material, is fabricated using the standard 0.18-μm CMOS technology. After serials of detailed experiments on the phase transition behaviors, we find that the RESET process is strongly dependent on the state of the inactive area and the active area affects the SET process dramatically. By applying a 5-mA current-voltage （I — V） sweep as initial operation, we can reduce the voltage drop beyond the active area during the RESET process and the overall RESET voltage decreases from 3 V plus to 2.5 V. For the SET operation, a non-cumulative programming method is introduced to eliminate the impact of randomly formed amorphous active area, which is strongly related to the threshold switching process and SET voltage. Combining the two methods, the endurance performance of the PCM device has been remarkably improved beyond 1 × 106 cycles.     

Properties of Seamless W Sub-Micro Electrode Used for Phase Change Memory

In order to improve the reliability of C-RAM devices, a seamless sub-micro W heating electrode in diameter 260 nm is fabricated with standard 0.18 μm CMOS processing line. Then we successfully manufacture a chalcogenide random access memory device using this seamless sub-micro W heating electrode. The results show good electrical performance, e.g. the reset current of 1.3mA and the set/reset cycle up to 10^9 have been achieved.     

Ge1Sb2Te4 Based Chalcogenide Random Access Memory Array Fabricated by 0.18-μm CMOS Technology

Ge1Sb2Te4-based chalcogenide random access memory array, with a tungsten heating electrode of 260hm in diameter, is fabricated by 0.18-μm CMOS technology. Electrical performance of the device, as web as physical and electrical properties of GelSb2 Te4 thin film, is characterized. SET and RESET programming currents are 1.6 and 4.1 mA, respectively, when pulse width is 100 ns. Both the values are larger than those of the Ge2Sb2 Tesbased ones with the same structure and contact size. Endurance up to 106 cycles with a resistance ratio of about 100 has been achieved.