倒装芯片上金属布线/凸点互连结构中原子的定向扩散

采用倒装芯片互连凸点串联回路研究了高温、高电流密度条件下倒装芯片上金属布线/凸点互连结构中原子的定向扩散现象,分析了互连结构中受电应力和化学势梯度作用的各相金属原子的扩散行为.在电迁移主导作用下,Ni(V)镀层中的Ni原子的快速扩散导致原本较为稳定的Ni(V)扩散阻挡层发生快速的界面反应,造成Al互连金属与焊料的直接接触.Al原子在电子风力作用下沿电子流方向向下迁移造成窗口附近焊料中Al原子含量逐步上升,同时,空位的反向迁移、聚集形成过饱和,导致Al互连中形成大面积空洞.焊料中的Sn,Pb原子在化学势梯度 关键词： 倒装芯片 凸点 电迁移 扩散     

热迁移对Cu/Sn/Cu焊点液-固界面Cu6Sn5生长动力学的影响

电子封装技术中, 微互连焊点在一定温度梯度下将发生金属原子的热迁移现象, 显著影响界面金属间化合物的生长和基体金属的溶解行为. 采用Cu/Sn/Cu焊点在250℃和280℃下进行等温时效和热台回流, 对比研究了热迁移对液-固界面Cu₆Sn₅生长动力学的影响. 等温时效条件下, 界面Cu₆Sn₅生长服从抛物线规律, 由体扩散控制. 温度梯度作用下, 焊点冷、热端界面Cu₆Sn₅表现出非对称性生长, 冷端界面Cu₆Sn₅生长受到促进并服从直线规律, 由反应控制, 而热端界面Cu₆Sn₅生长受到抑制并服从抛物线规律, 由晶界扩散控制. 热端Cu 基体溶解到液态Sn中的Cu原子在温度梯度作用下不断向冷端热迁移, 为冷端界面Cu₆Sn₅的快速生长提供Cu 原子通量. 计算获得250℃和280℃下Cu原子在液态Sn中的摩尔传递热Q^*分别为14.11和14.44 kJ/mol, 热迁移驱动力F_L分别为1.62×10^-19和1.70×10^-19 N.     

基于微观结构的Cu互连电迁移失效研究

提出了一种基于微观晶粒尺寸分布的Cu互连电迁移失效寿命模型. 结合透射电子显微镜和统计失效分析技术, 研究了Cu互连电迁移失效尺寸缩小和临界长度效应及其物理机制. 研究表明, 当互连线宽度减小, 其平均晶粒尺寸下降并导致互连电迁移寿命降低. 小于临界长度的互连线无法提供足够的空位使得铜晶粒耗尽而发生失效. 当互连长度大于该临界长度时, 在整个电迁移测试时间内, 部分体积较小的阴极端铜晶粒出现耗尽情况. 随着互连长度的增加该失效比例迅速增大, 电迁移失效寿命减小. 当互连长度远大于扩散长度时, 失效时间主要取决于铜晶粒的尺寸, 且失效寿命和比例随晶粒尺寸变化呈现饱和的波动状态. 关键词： Cu 互连 电迁移 微观结构     

热-电应力下Cu/Ni/SnAg_(1.8)/Cu倒装铜柱凸点界面行为及失效机理

微互连铜柱凸点因其密度高、导电性好、噪声小被广泛应用于存储芯片、高性能计算芯片等封装领域,研究铜柱凸点界面行为对明确其失效机理和组织演变规律、提升倒装封装可靠性具有重要意义.采用热电应力实验、在线电学监测、红外热像测试和微观组织分析等方法,研究Cu/Ni/SnAg_1.8/Cu微互连倒装铜凸点在温度100—150℃、电流密度2×10~4—3×10~4 A/cm~2热电应力下的互连界面行为、寿命分布、失效机理及其影响因素.铜柱凸点在热电应力下的界面行为可分为Cu_6Sn_5生长和Sn焊料消耗、Cu_6Sn_5转化成Cu_3Sn、空洞形成及裂纹扩展3个阶段,Cu_6Sn_5转化为Cu_3Sn的速率与电流密度正相关.热电应力下,铜凸点互连存在Cu焊盘消耗、焊料完全合金化成Cu_3Sn、阴极镍镀层侵蚀和层状空洞4种失效模式.基板侧Cu焊盘和铜柱侧Ni镀层的溶解消耗具有极性效应,当Cu焊盘位于阴极时,电迁移方向与热迁移方向相同,加速Cu焊盘的溶解以及Cu_3Sn生长,当Ni层为阴极时,电迁移促进Ni层的消耗,在150℃,2.5×10~4 A/cm~2下经历2.5h后,Ni阻挡层出现溃口,导致Ni层一侧的铜柱基材迅速转化成(Cu_x,Ni_y)_6Sn_5和Cu_3Sn合金.铜柱凸点互连寿命较好地服从2参数威布尔分布,形状参数为7.78,为典型的累积耗损失效特征.研究结果表明:相比单一高温应力,热电综合应力显著加速并改变了铜柱互连界面金属间化合物的生长行为和失效机制.     

金属互连电迁移噪声的分形特征

为了研究金属互连电迁移失效机理并寻找新的电迁移表征参量，应用分形理论，通过电子扩散轨迹分形维数，将电迁移噪声时间序列分形维数与晶粒间界分形维数相联系，确定了噪声时间序列分形维数在电迁移演变中的变化趋势.研究结果表明，在金属互连电迁移前期，晶粒间界形貌越来越复杂，致使噪声时间序列的分形维数逐渐增大；成核后，由于空位凝聚成空洞，晶粒间界形貌变得较成核前规则，致使噪声时间序列的分形维数减小；成核时刻是其折点.实验结果证明理论分析的正确性，噪声时间序列的分形维数可望作为金属互连电迁演变的表征参量.     

金属-氧化物-半导体硅发光器件在集成电路中的应用前景

集成硅光电子学的目的之一就是为大众市场创造应用广泛、成本低廉的光子互连工具.随着摩尔定律逼近理论极限,集成芯片的金属互连越来越跟不上芯片体积微型化、频率高速化和功耗分配精益化的需求.本文基于硅基发光器件的发展历程,详细论证了金属-氧化物-半导体结构硅发光器件在未来集成电路中的合理应用,提出了全硅光电集成电路在理论和工艺上的可行性.这种电路突破了传统芯片电互连码之间串扰的瓶颈,改善之后的互连速度理论可达光速,有望成为新一代集成芯片的主流.     

金属原子催化作用下缺陷石墨烯薄膜的自修复过程

采用分子动力学方法,模拟了金属原子存在条件下缺陷石墨烯的自修复过程.模拟采用了Ni和Pt两种金属原子作为催化剂,通过改变系统温度,得到了多组模拟结果.观察对比了模拟结束时获得的原子构型图,并通过计算修复过程中石墨烯内5,6,7元环的数量变化,研究了不同金属原子对缺陷石墨烯的催化修复效果,发现在适当的温度(1600 K和2000 K)下,与无金属原子条件下的修复结果相比,两种金属原子都表现出了一定的催化修复能力,且Ni表现出的催化修复能力要优于Pt.为了探究其背后的机理,我们模拟了部分典型的结构演变.发现Ni和Pt原子分别会导致"环内跳出"和"断环"的局部结构转变,并且在不同温度下均表现出不同程度捕获碳链的能力.此外,观察了两种金属原子在平面内外的不同迁移行为,并通过绘制金属原子的迁移路线,计算其迁移量,进一步研究了两种金属原子不同的催化修复机理.研究结果有利于认识不同金属原子具有的不同催化修复效果,理解不同金属原子的催化作用机制,有助于针对缺陷石墨烯的修复选择合适的催化剂.     

铜互连电迁移失效阻变特性研究

基于铜互连电迁移失效微观机理分析建立一种Cu／SiCN互连电迁移失效阻变模型，并提出一种由互连阻变曲线特征参数即跳变台阶高度与斜率来获取失效物理参数的提取方法．研究结果表明，铜互连电迁移失效时间由一定电应力条件下互连阴极末端晶粒耗尽时间决定．铜互连电迁移失效一般分为沟槽型和狭缝型两种失效模式．沟槽型空洞失效模式对应的阻变曲线一般包括跳变台阶区和线性区两个特征区域．晶粒尺寸分布与临界空洞长度均符合正态对数分布且分布参数基本一致．阻变曲线线性区斜率与温度呈指数函数关系．利用阻变模型提取获得的电迁移扩散激活能约为0．9eV,与Black方法基本一致．     

有丢失物缺陷的铜互连线中位寿命的定量研究

本文研究了六层互连线上的丢失物缺陷对互连电迁移中位寿命的影响,提出了各层互连线缺陷处的温度模型和缺陷在不同互连层的中位寿命模型,能够定量地计算缺陷对互连电迁移中位寿命的影响,给出了提高互连线中位寿命的方法.研究结果表明：互连线宽度与缺陷处互连线有效宽度的比值越大,互连线寿命越短;缺陷处的温度越高,互连线寿命越短.在互连线参数变化明显的层与层之间,互连线寿命受比值和温度的双重影响,寿命急剧下降.根据该物理模型可以准确计算出互连线具体的温度和寿命数据,可以直接指导集成电路的设计和工艺制造. 关键词： 丢失物缺陷 中位寿命 可靠性 铜互连     

基于原子运动模型的类金刚石薄膜生长机理研究

利用分子动力学模拟方法，从原子尺度上研究了类金刚石(DLC)薄膜生长过程. 按照运动特点把入射原子在表面的行为分为表面冷冻、迁移、注入和反弹等四种，并由此提出原子运动模型. 入射原子的表面行为对DLC薄膜的微观结构以及生长方式有重要影响. 其中原子水平迁移是薄膜热弛豫的主要途径，入射原子的注入和迁移行为相互竞争，决定了薄膜生长的模式和最终结构. 利用统计分析手段给出了入射能量对原子表面行为进而对薄膜结构的影响，加深了对DLC薄膜生长机理的认识.     

Effect of alternating electric current on the nanoindentation of copper

Electromechanical interaction determines the structural reliability of electronic interconnects. Using the nanoindentation technique, the effect of alternating electric current on the indentation deformation of copper strips was studied for the indentation load in a range of 100 to 1600???N at room temperature. During the test, an alternating electric current of the electric current density in a range of 1.25 to 4.88?kA/cm² was passed through the copper strips. The indentation results showed that the reduced contact modulus decreased linearly with increasing the electric current density. The indentation hardness decreased with increasing the indentation deformation, demonstrating the normal indentation size effect. Using the model of strain gradient plasticity, we found that the strain gradient underneath the indentation decreased slightly with increasing the electric current density for the same indentation depth.     

高速光通讯面发射激光器的热分析及优化

垂直腔面发射激光器(VCSEL)已成为短距离数据通信传输系统的首选光源。热限制是VCSEL器件调制带宽进一步增加的一个主要的制约因素。本文基于有限元分析的方法对影响980 nm-VCSEL器件有源区温度的参数,如驱动电流、氧化孔径尺寸、氧化层材料等做了比较分析,还数值分析了二元系Ga As/Al As材料DBR用于高速低能耗VCSEL器件的优势,为绿色光子器件设计提供优化思路。     

The role of nonlinear diode laser amplifiers in optical processors and interconnects

The advantages to be gained from the use of optical processors and interconnects for hybrid electronic/optical signal processing networks are first presented. The physics of nonlinear diode laser amplifiers is then examined in the context of optical thresholding and logic. Specific examples of the use of these devices in simple optical processors and interconnects are proposed. The technology required for realization of arrays of laser amplifiers for the proposed applications is finally discussed.     

A novel analytical thermal model for multilevel nano-scale interconnects considering the via effect

Based on the heat diffusion equation of multilevel interconnects, a novel analytical thermal model for multilevel nano-scale interconnects considering the via effect is presented, which can compute quickly the temperature of multilevel interconnects, with substrate temperature given. Based on the proposed model and the 65~nm complementary metal oxide semiconductor (CMOS) process parameter, the temperature of nano-scale interconnects is computed. The computed results show that the via effect has a great effect on local interconnects, but the reduction of thermal conductivity has little effect on local interconnects. With the reduction of thermal conductivity or the increase of current density, however, the temperature of global interconnects rises greatly, which can result in a great deterioration in their performance. The proposed model can be applied to computer aided design (CAD) of very large-scale integrated circuits (VLSIs) in nano-scale technologies.     

An RLC interconnect analyzable crosstalk model considering self-heating effect

According to the thermal profile of actual multilevel interconnects, in this paper we propose a temperature distribution model of multilevel interconnects and derive an analytical crosstalk model for the distributed resistance-inductance-capacitance (RLC) interconnect considering effect of thermal profile. According to the 65-nm complementary metal-oxide semiconductor (CMOS) process, we compare the proposed RLC analytical crosstalk model with the Hspice simulation results for different interconnect coupling conditions and the absolute error is within 6.5%. The computed results of the proposed analytical crosstalk model show that RCL crosstalk decreases with the increase of current density and increases with the increase of insulator thickness. This analytical crosstalk model can be applied to the electronic design automation (EDA) and the design optimization for nanometer CMOS integrated circuits.     

Erratum to: Multiple magnetic transitions in single crystals of Ce12Fe57.5As41and La12Fe57.5As41

Commercial computers based on electronic logic devices have brought great changes to the world. However, traditional electronic devices are suffering from numerous technical challenges in their attempts to continue to satisfy Moore's law. Alloptical logic devices, as promising successors to their electronic counterparts, have become a major focus of optics research. In this paper, we provide a review of current all-optical logic devices. The logic gates in these devices, which are described in the first part of the review, are divided into five categories based on the different principles used in their realization. Complex optical devices with various functions and reconfigurable devices are summarized in the next section. In the final part of this paper, we discuss some of the previous works on all-optical integrated chips with specific functions. This review will provide a complete technological roadmap for all-optical devices and aims to be helpful in possible future developments in this growing field.     

Structural stability and theoretical strength of Cu crystal under equal biaxial loading

Cu has been used extensively to replace Al as interconnects in ULSI and MEMS devices. However, because of the difference in the thermal expansion coefficients between the Cu film and the Si substrate, large biaxial stresses will be generated in the Cu film. Thus, the Cu film becomes unstable and even changes its morphologies which affects the device manufacturing yield and ultimate reliability. The structural stability and theoretical strength of Cu crystal under equal biaxial loading have been investigated by combining the MAEAM with Milstein-modified Born stability criteria. The results indicate that, under sufficient tension, there exists a stress-free BCC phase which is unstable and slips spontaneously to a stress-free metastable BCT phase by consuming internal energy. The stable region ranges from −15.131 GPa to 2.803 GPa in the theoretical strength or from −5.801% to 4.972% in the strain respectively.     

Manipulation of oxide surfaces

Metal oxides have considerable potential as insulating supports for nanoscale electronic devices. One of the key attributes of metal oxide surfaces is their capacity to be modified by electron beams and scanning probe tips. Such modifications can involve the creation of O vacancies or an area of a different reconstruction, which in principle can act as anchoring points or templates for molecules or metal interconnects. In this Prospective we describe previous attempts at well-defined modification in order to illustrate this potential.