Ka/Q band GaAs IMPATT amplifier technology

GaAs IMPATT diodes are capable of generating 2 to 3 W simultaneously with 18–22% efficiency in the 33 GHz to 46 GHz frequency band. The design of the amplifier circuits which utilize these devices is discussed. The circuit design is based on a 3-step closed form algorithm. The first step is a passive circuit characterization with an automatic network analyzer. In the second step, a computer is used to generate diode device lines. The third step is load line synthesis for predictable operation. The resulting performance is described. 2 W over a 2GHz bandwidth was achieved simultaneously with a minimum gain of 12 dB.     

一种新型的四维多翼超混沌吸引子及其在图像加密中的研究

提出了一种新的能产生多翼混沌吸引子的四维混沌系统,该系统在不同的参数条件下能产生混沌、超混沌吸引子.然后对此混沌系统的一些基本的动力学特性进行了理论分析和数值仿真,如平衡点、Poincaré映射、耗散性、功率谱、Lyapunov指数谱、分岔图等.同时设计了一个模拟振荡电路实现四翼超混沌吸引子,硬件电路模拟实验结果与数值仿真结果相一致.最后将此四维多翼超混沌系统用于物理混沌加密和高级加密标准加密级联的混合图像加密算法,这种利用物理混沌不可预测性的混合加密系统,不存在确定的明文密文映射关系,且密文统计特性也比其他加密系统要好.     

A quantum circuit design of AES requiring fewer quantum qubits and gate operations

Advanced Encryption Standard (AES) is one of the most widely used block ciphers nowadays, and has been established as an encryption standard in 2001. Here we design AES-128 and the sample-AES (S-AES) quantum circuits for deciphering. In the quantum circuit of AES-128, we perform an affine transformation for the SubBytes part to solve the problem that the initial state of the output qubits in SubBytes is not the |0>^⊗8 state. After that, we are able to encode the new round sub-key on the qubits encoding the previous round sub-key, and this improvement reduces the number of qubits used by 224 compared with Langenberg et al.’s implementation. For S-AES, a complete quantum circuit is presented with only 48 qubits, which is already within the reach of existing noisy intermediate-scale quantum computers.     

Development of highly integrated RSFQ circuits on the basis of intrinsically shunted Josephson junctions

At PTB, for application in rapid single flux quantum (RSFQ) and voltage standard circuits, the development of highly integrated SDE circuits is focused on devices based on intrinsically shunted Josephson junctions in the SINIS and SNS technologies. In SINIS technology, the fabrication process has been optimized to values of the critical current density of j_C=500 A/cm² and the characteristic voltage of V_C=190 μV. To raise the circuit integration level, successive steps of development are shown by the example of the layout of an elementary RSFQ cell designed for higher values of j_C. In SNS technology, a fabrication process has been developed to produce small ramp-type junctions with contact areas smaller than 0.4 μm² and with values for j_C and V_C of about j_C=200 kA/cm² and V_C=20 μV. The design allows the SNS junction size to be further reduced down to the deep sub-micron range.     

Lightweight secure image encryption scheme based on chaotic differential equation

The ultimate secure choice for block cryptosystem until now is advanced encryption standard (AES). It is very difficult to implement AES for the constrained situations such as sensor networks, image encryption and RFID tags. In this article, a chaotic oscillator generated by a second order differential equation is used to produce confusion and diffusion in the plaintext message to achieve the desired secrecy. The produced chaotic sequence of random numbers from dynamical system is utilized to scramble the pixels of an image to obtain an encrypted image. Chaos based encryption technique is found secure enough to tackle chosen plaintext attacks and brute force attacks. The specific attributes of chaotic system like, sensitivity to initial conditions, randomness and uncertainty make it suitable for the design of cryptosystem. The dominance of the proposed scheme is acknowledged due to the fact of better cryptographic properties when compared with the algorithms already developed in the literature.     

Design of Low-Profile Millimeter-Wave Substrate Integrated Waveguide Power Divider/Combiner

A low-profile millimeter-wave substrate integrated waveguide (SIW) power divider/combiner is presented in this paper. The simplified model of this compact SIW power dividing/combining structure has been developed. Analysis based on equivalent circuits gives the design formula for perfect power dividing/combining. In order to verify the validity of the design method, a four-way SIW power divider/combiner circuit operating at Ka band is designed, fabricated and measured. Good agreement between simulated and measured results is found for the proposed passive power divider/combiner. Experiments on the four-way passive divider/combiner back-to-back design demonstrate a minimum overall insertion loss of 1.5 dB at 31.1 GHz, corresponding to a power-combining efficiency of 84%. The measured 10-dB return loss bandwidth is demonstrated to be 2.2 GHz, and its 0.5-dB bandwidth was 2 GHz.     

A high efficiency 46 to 92 GHz all microstrip frequency doubler

Using packaged GaAs varactor diodes, a high efficiency 46 to 92 GHz frequency doubler has been developed. Microstrip circuits have been used to match the input and output impedances presented by the diode. A conversion loss of 8 to 10 dB was measured. This doubler circuit is useful for W-band (75 to 110 GHz) integrated circuit receivers and transceivers. The use of microstrip circuit can drastically reduce the fabrication cost in addition to size and weight.     

Statistical modeling of inductances in high-Tc superconductor electronic structures

In the design of electronic applications, e.g. rapid single flux quantum (RSFQ) circuits, with high-T_c superconductors there is an obvious necessity of having precise knowledge of loop inductances. In general, these inductances have to be computed numerically due to the small sizes of the structures and the large contribution of the kinetic inductance. The present work is based on the analysis of a large number of inductances which have been calculated numerically for several high-T_c superconducting loop configurations. By means of statistical modeling, analytical formulae, which are customized for the considered type of structure, are derived. They can efficiently be used to simplify and accelerate the process of layout design in high-T_c RSFQ electronics.     

基于CSMRC结构和容性肖特基二极管的220GHz三倍频器

设计了基于容性肖特基二极管的220 GHz非平衡三倍频器。首先对容性肖特基二极管进行测试和关键参数提取,建立了肖特基二极管的等效电路模型,以此为基础进行三倍频电路设计;在倍频电路设计中通过引入紧凑悬置微带谐振单元(CSMRC)滤波结构来减小信号传输损耗;由于三倍频电路设计中难以实现全波阻抗匹配,因此采用了整体电路结构谐波平衡调匹配方法设计倍频电路,最后对制备出的倍频器进行测试和分析;实验测试结果表明:倍频器在213.1~221.6 GHz范围内输出功率大于10 mW,倍频效率大于5%,最高输出功率为18.7 mW@218.6 GHz,最高倍频效率为8.24%@217.9 GHz。     

Low-pass and high-pass filters using coaxial-type dielectric resonators

This paper proposes new low-pass and high-pass filters using coaxial-type dielectric resonators. The low-pass filter has a LC-type circuit structure and is composed of three inductances and two resonance circuits. The resonance circuits are the open-ended coaxial-type dielectric resonators whose length is g/4. The high-pass filter has a CL-type circuit structure. Two high-pass filters are described, one of them is composed of three capacitances andtwo resonance circuits, the other is composed of five capacitances and four resonance circuits. The operating frequency range of the low-pass filter is 0.13–0.9 GHz and the cutoffency is 900 MHz, and the insertion loss is 0.3 dB. The corresponding quantities of the high-pass filter are 0.9–2.5 GHz, 900 MHz, and 0.3 dB, respectively.     

RSFQ的初步研究

RSFQ应用于高速电子计算机是近年来活跃在低温超导电子学领域的新兴课题。文中从约瑟夫逊效应的等效模型出发 ,阐述了 RSFQ电路的基本基理及基于节点约瑟夫逊相位的数值模拟方法 ,并把它用于一个 RSFQ单向缓冲器的瞬态分析 ,给出了其相位和电压波形     

A dual band CMOS VCO with a balanced duty cycle buffer

This paper proposes a dual band VCO with a standard 0.35 μm CMOS process to generate 1.07 and 2.07 GHz. The proposed VCO architecture with 50% duty cycle circuit and a half adder (HA) is able to produce a frequency two times higher than that of the conventional VCOs. The measurement results demonstrate that the gain of VCO and power dissipation are 561 MHz/V and 14.6 mW, respectively. The phase noises of the dual band VCO are measured to be −102.55 and −95.88 dBc/Hz at 2 MHz offset from 1.07 and 2.07 GHz, respectively.     

Experimental investigation of millimeter wave Gunn oscillator circuits in circular waveguides

Millimeter wave Gunn oscillator circuits using circular waveguides for 33–50 GHz and 75–110 GHz frequency bands are described. These oscillators are simpler to construct at millimeter wavelengths compared to the conventional rectangular waveguide circuits. The effect of various circuit parameters on the oscillator frequency and output power has been experimentally studied. The CW power and mechanical tuning range obtained from the circular waveguide Gunn oscillators are found to be comparable and sometimes even better than those obtained with conventional rectangular waveguide circuits using the same Gunn device.     

热电制冷LED自然对流散热的设计与优化

为提升高热流密度下LED灯具的自然对流散热性能,以一款基于热电制冷（TEC）的单颗LED小型灯具模组为研究对象,在采用实验测量和回归拟合准确获得TEC性能参数的基础上,建立了有无TEC参与散热的等效热路模型,并选择合理的数学公式对其进行性能描述,进而遵循本文设计的计算流程快速得到各种散热性能数据。LED模组的散热分析表明：在恒定的LED热功率下,施加最佳的TEC电流可获得最高的散热性能;LED热功率越低,安装TEC的散热性能越比常规方法优异。经遗传算法优化前后的性能对比分析表明：优化后结构中TEC的合理工作区明显增大,能满足LED更高功率的散热需求;当LED为0.493 W时,优化后结构的最佳结温仅为15.66℃,远低于30℃的环境温度。基于TEC实验数据建立的等效热路模型,能为装配TEC的LED模组提供快速完整的散热设计分析与结构优化的合理方案。     

宽输出电压的半导体激光器驱动电源研究

介绍了一种大功率、宽输出电压范围的半导体激光器脉冲驱动电源的设计方法。根据半导体激光器脉冲驱动电源高电压、大电流的工作特性需求,脉冲放电环节采用多模块级联与功率开关管线性控制脉冲放电相结合的拓扑结构,这样既实现了脉冲电流平滑稳定,又提高了输出电压等级与功率。充电环节采取LCC谐振变换器结构,其抗负载短路和开路的能力非常适用于脉冲放电场合。该脉冲电源输出参数为:电压0~1000 V,电流1~160 A,脉宽200~250 μs,频率100 Hz内可调,具备较宽泛灵活的输出范围,可适应不同规模的激光二极管阵列。最后,分别通过单模块、两模块与三模块小功率级联型驱动实验验证了采用多模块级联与功率开关管线性控制脉冲放电相结合方法的可行性。     

一款2 G/s采样率20 GHz带宽主从式跟踪保持电路设计研究

设计了一款全差分、20 GHz带宽主从式跟踪保持芯片(MS-THA)。该芯片采样率为2 G/s,工作带宽大于20 GHz,采用0.13μm SiGe BiCMOS工艺实现。该芯片采用传统的开关发射极跟随器(SEF)作为跟踪保持核心电路,Cherryhooper电路作为输入缓冲和输出缓冲的带宽增强核心电路,并利用交叉反馈电容抑制馈通。为了验证上述电路的有效性,设计了一个单级THA电路,测试结果为MS-THA电路提供了足够的支持。在单电源+3.3 V供电、输入直流电平为0 V,2 G/s采样率以及-3 dBm输入信号功率条件下,获得的单端输出无杂散动态范围小于-23.5 dB,总功耗约为300 mW。     

超导数字计算机

超导数字计算机是下世纪超级机的发展方向 ,它在计算机科学发展的历史上将具有十分重要的意义,文章简要介绍了快速单磁通量子（ＲＳＦＱ）超导计算机研究的发展、ＲＳＦＱ逻辑电路的基本原理、超导计算机的基本结构以及超导数字计算机的展望。     

不同频率高功率微波辐照下PCB电路的混合模拟

采用一个混合模拟方法研究计算了不同频率高功率微波(HPM)辐照下含有PIN限幅器的PCB电路上的耦合信号。该混合模拟方法基于瞬态电磁拓扑和器件/电路混合模拟技术,实现了场、路、器件的混合模拟,能够模拟计算出HPM辐照下屏蔽腔内PCB电路上的耦合信号。用该方法研究计算了频率分别为1,1.25和2.5 GHz的HPM在PCB电路上的耦合信号。计算结果表明:当PCB电路无屏蔽腔时,1 GHz HPM的耦合信号最大,而PCB电路有屏蔽腔时,2.5 GHz HPM的耦合信号最大;PIN限幅器在耦合信号较大时具有较好的抑制作用。     

OEIC technologies for high-speed optical interconnection system

As the level of integration and the power of computation increase, methods of interconnecting computational elements attract more attention and the total system performance is bottlenecked by the problems associated with electrical interconnections. Optical interconnections have advantages of practically unlimited bandwidth and absence of crosstalk. To utilize such merits of optical interconnections, a large number of low-cost high-performance optoelectronic integrated circuits (OEICs) are needed. This paper focuses on monolithically integrated receiver OEICs that consist of InP/InGaAs p-i-n photodiodes and fully ion-implanted InP junction field-effect transistors (JFETs). In the formation of shallow InP p-n junctions we use a co-implantation technique in which we implant a group V element together with Be, a dopant, and take advantage of damage and stoichiometry effects. We fabricate a p-i-n/JFET amplifier receiver front-end circuit and a receiver 2×2 crosspoint switch circuit using this technique. We also develop bandwidth enhancement designs using inductive peaking and cascoding. Finally, we demonstrate a single-channel, free-space optical interconnection system with a bandwidth of 1.5 GHz and an interconnection length of 50 cm.     

Sliding backshorts for planar circuits

The Superconductor-Insulator-Superconductor (SIS) tunnel junction is an extremely sensitive heterodyne detector at millimeter and submillimeter wavelengths. The large inherent capacitance associated with this device results in a substantial impedance mismatch with typical antennas and, therefore, requires a tuning circuit for optimum results. At frequencies where waveguide dimensions are realizable, impedance matching can be accomplished by embedding the detector in a waveguide circuit with adjustable waveguide backshorts. At higher frequencies, where waveguide dimensions become prohibitively small, a planar transmission line embedding circuit provides a reasonable alternative. Typically, such planar circuits offer no post-fabrication adjustability, resulting in demanding materials and design requirements. An adjustable planar embedding circuit based on coplanar transmission lines with movable noncontacting shorting elements has been developed. The shorting elements each consist of a thin metallic plate with an optimized arrangement of rectangular holes, placed along the insulated metallic transmission line to provide a periodic variation of the line impedance. A scadel (1–5 GHz) has shown that a large reflection coefficient, |s ₁₁|–0.5 dB, can be achieved with these sliding elements. A low frequency tuning circuit incorporating these shorting elements has been tested to demonstrate practical tuning ranges.