Ultrathin gate dielectrics for silicon nanodevices

This paper reviews recent progress in structural and electronic characterizations of ultrathin SiO₂thermally grown on Si(100) surfaces and applications of such nanometer-thick gate oxides to advanced MOSFETs and quantum-dot MOS memory devices. Based on an accurate energy band profile determined for the n ⁺ -poly- Si/SiO₂/Si(100) system, the measured tunnel current through ultrathin gate oxides has been quantitatively explained by theory. From the detailed analysis of MOSFET characteristics, the scaling limit of gate oxide thickness is found to be 0.8 nm. Novel MOSFETs with a silicon quantum-dot floating gate embedded in the gate oxide have indicated the multiple-step electron injection to the dot, being interpreted in terms of Coulombic interaction among charged dots.     

Physics of fluctuation processes in downscaled silicon MOSFETs

Physical mechanics of fluctuation processes in advanced submicron and decananometer MOSFETs (metal-oxide-semiconductor field-effect transistors) including the ultra-thin film SOI (siliconon-insulator) devices using strained silicon films are reviewed. The review is substantially based on the results obtained by the authors. It is shown that the following drastic changes occur in the nature and parameters of noise in such devices as a result of their downscaling when the gate oxide thickness and the channel length and width are decreased, the SOI substrates are used, the silicon film thickness is reduced, the film doping level is varied, the strained silicon films are employed, etc. Firstly, the Lorentzian components can appear in the current noise spectra. Those components are due to (i) electron tunneling from the valence band through the gate oxide in the SOI MOSFETs of a sufficiently thin gate oxide (LKE-Lorentzians); (ii) Nyquist fluctuations generated in the source and drain regions near the back Si/SiO₂ interface in the SOI MOSFETs (BGI Lorentzians); (iii) electron exchange between the channel and some single trap in the gate oxide of the transistors with sufficiently small length and width of the channel (RTS Lorentzians). Secondly, the 1/f-noise level can increase due to (i) the appearance of recombination processes near the Si/SiO₂ interface activated by the currents of electron tunneling from the valence band; (ii) an increase in the trap density in the gate oxide of the devices fabricated on the biaxially tensile-strained silicon films; (iii) the contribution of the 1/f fluctuations of the current flowing through the gate oxide as a result of electron tunneling from the conduction band. At the same time, the 1/f-noise level may decrease due to a decrease in the trap density in the gate oxide of the transistors fabricated on the uniaxially tensile-strained silicon films. Moreover, a 1/f ^1.7 component may appear in the noise spectra for the transistors of a sufficiently thin gate oxide, whose component is due to charge fluctuations on the defects located near the interface between the gate polysilicon and the gate oxide.     

TEOS-based low-pressure chemical vapor deposition for gate oxides in 4H–SiC MOSFETs using nitric oxide post-deposition annealing

The use of SiO₂/4H–SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) can be problematic due to high interface state density (D_it) and low field-effect mobility (μ_fe). Here, we present a tetra-ethyl-ortho-silicate (TEOS)-based low-pressure chemical vapor deposition (LPCVD) method for fabricating the gate oxide of 4H–SiC MOSFETs using nitric oxide post-deposition annealing. SiO₂/4H–SiC MOS capacitors and MOSFETs were fabricated using conventional wet and TEOS oxides. The measured effective oxide charge density (Q_eff) and D_it of the TEOS-based LPCVD SiO₂/4H–SiC MOS capacitor with nitridation were 4.27 × 10¹¹ cm⁻² and 2.99 × 10¹¹ cm⁻²eV⁻¹, respectively. We propose that the oxide breakdown field and barrier height were dependent on the effective Q_eff. The measured μ_fe values of the SiO₂/4H–SiC MOSFETs with wet and TEOS oxides after nitridation were, respectively, 11.0 and 17.8 cm²/V due to the stable nitrided interface between SiO₂ and 4H–SiC. The proposed gate stack is suitable for 4H–SiC power MOSFETs.     

埋氧注氮工艺对部分耗尽SOI PMOSFET顶栅氧的辐射硬度的影响

研究了埋氧注氮对部分耗尽SOI PMOSFET顶栅氧的总剂量辐射硬度所造成的影响。注入埋氧的氮剂量分别是8×1015 , 2×1016 和1×1017cm-2。实验结果表明，辐照前，晶体管的阈值电压随氮注入剂量的增加向负方向漂移。在正2V的栅偏压下，经5×105 rad(Si)的总剂量辐照后，同埋氧未注氮的晶体管相比，埋氧注氮剂量为8×1015 cm-2的晶体管呈现出了较小的阈值电压漂移量。然而，当注氮剂量高达2×1016 和 1×1017cm-2时，所测大多数晶体管的顶栅氧却由于5×105 rad(Si)的总剂量辐照而受到了严重损伤。另外，对于顶栅氧严重受损的晶体管，其体-漏结也受到了损伤。所有的实验结果可通过氮注入过程中对顶硅的晶格损伤来解释。     

电离辐射对部分耗尽绝缘体上硅器件低频噪声特性的影响

本文针对辐射前后部分耗尽结构绝缘体上硅(SOI)器件的电学特性与低频噪声特性开展试验研究. 受辐射诱生埋氧化层固定电荷与界面态的影响, 当辐射总剂量达到1 M rad(Si) (1 rad = 10^-2 Gy)条件下, SOI器件背栅阈值电压从44.72 V 减小至12.88 V、表面电子有效迁移率从473.7 cm²/V·s降低至419.8 cm²/V· s、亚阈斜率从2.47 V/dec增加至3.93 V/dec; 基于辐射前后亚阈斜率及阈值电压的变化, 可提取得到辐射诱生界面态与氧化层固定电荷密度分别为5.33×10¹¹ cm^{- 2}与2.36×10¹² cm^-2. 受辐射在埋氧化层-硅界面处诱生边界陷阱、氧化层固定电荷与界面态的影响, 辐射后埋氧化层-硅界面处电子被陷阱俘获/释放的行为加剧, 造成SOI 器件背栅平带电压噪声功率谱密度由7×10^{- 10} V²·Hz^-1增加至1.8×10^-9 V² ·Hz^-1; 基于载流子数随机涨落模型可提取得到辐射前后SOI器件埋氧化层界面附近缺陷态密度之和约为1.42×10¹⁷ cm^-3·eV^-1和3.66×10¹⁷ cm^-3·eV^-1. 考虑隧穿削弱因子、隧穿距离与时间常数之间关系, 本文计算得到辐射前后埋氧化层内陷阱电荷密度随空间分布的变化.     

Investigation of gate current in nano-scale MOSFETs by Monte Carlo solution of quantum Boltzmann equation

This paper investigates gate current through ultra-thin gate oxide of nano-scale metal oxide semiconductor field effect transistors (MOSFETs), using two-dimensional (2D) full-band self-consistent ensemble Monte Carlo method based on solving quantum Boltzmann equation. Direct tunnelling, Fowler--Nordheim tunnelling and thermionic emission currents have been taken into account for the calculation of total gate current. The 2D effect on the gate current is investigated by including the details of the energy distribution for electron tunnelling through the barrier. In order to investigate the properties of nano scale MOSFETs, it is necessary to simulate gate tunnelling current in 2D including non-equilibrium transport.     

Comparison of effect of 5 MeV proton and Co-60 gamma irradiation on silicon NPN rf power transistors and N–channel depletion MOSFETs

NPN transistors and N-channel depletion metal oxide semiconductor field effect transistors (MOSFETs) were irradiated with 5?MeV protons and ⁶⁰Co gamma radiation in the dose ranging from 1?Mrad(Si) to 100?Mrad(Si). The different electrical characteristics of the NPN transistor such as Gummel characteristics, excess base current (ΔI_B), dc current gain (h_FE), transconductance (g_m), displacement damage factor (K) and output characteristics were studied as a function of total dose. The different electrical characteristics of N-channel MOSFETs such as threshold voltage (V_th), density of interface trapped charges (ΔN_it), density of oxide trapped charges (ΔN_ot), transconductance (g_m), mobility (µ) and drain saturation current (I_DSat) were studied systematically before and after irradiation in the same dose ranges. A considerable increase in the base current (I_B) and decrease in the h_FE, g_m and collector saturation current (I_CSat) were observed after irradiation in the case of the NPN transistor. In the N-channel MOSFETs, the ΔN_it and ΔN_ot were found to increase and V_th, g_m, µ and I_DSat were found to decrease with increase in the radiation dose. The 5?MeV proton irradiation results of both the NPN transistor and N-channel MOSFETs were compared with ⁶⁰Co gamma-irradiated devices in the same dose ranges. It was observed that the degradation in 5?MeV proton-irradiated devices is more when compared with the ⁶⁰Co gamma-irradiated devices at higher total doses.     

Ge metal oxide semiconductor field effect transistors with optimized Si cap and HfSiO2 high-k metal gate stacks

High mobility metal-oxide-semiconductor-field-effect-transistors (MOSFETs) are demonstrated on high quality epitaxial Si_0.75Ge_0.25 films selectively grown on Si (100) substrates. With a Si cap processed on Si_0.75Ge_0.25 channels, HfSiO₂ high-k gate dielectrics exhibited low C–V hysteresis (<10 mV), interface trap density (7.5 × 10¹⁰), and gate leakage current (∼10⁻²A/cm² at an EOT of 13.4 Å), which are comparable to gate stack on Si channels. The mobility enhancement afforded intrinsically by the Si_0.75Ge_0.25 channel (60%) is further increased by a Si cap (40%) process, resulting in a combined ∼100% enhancement over Si channels. The Si cap process also mitigates the low potential barrier issues of Si_0.75Ge_0.25 channels, which are major causes of the high off-state current of small band gap energy Si_0.75Ge_0.25 pMOSFETs, by improving gate control over the channel.     

Three-dimensional electronic structures in the Si inversion layer of nanoscale metal-oxide-semiconductor field-effect transistors

The three-dimensional electronic structure in the Si inversion layer of nanoscale metal-oxide-semiconductor field-effect transistors (MOSFETs) were calculated by using a self-consistent method. The electronic energy states and the probability density functions in a three-dimensionally confined quantum structure were determined. The energy states strongly depended on the thickness of the thin oxide layer and the applied gate voltage. The few electrons occupying the Si inversion layer significantly affected the electric potential profile of the inversion layer, and a small variation in the oxide thickness dramatically changed the electronic properties in the Si inversion layer. These results can help in understanding the electronic structures in Si inversion layers of nanoscale MOSFETs.