制造单元布局问题的双目标模型与算法研究

单元制造系统的布局对于提高系统的效率起着十分重要的作用。以最小化物料周转量和设施面积为目标,建立了一个单元制造系统布局的双目标优化模型,在该模型中不同制造单元的布局、单元内部不同设施的位置与方向这几个问题可以同时进行优化。基于模拟退火邻域解的变尺度生成机制和双目标抽样准则设计了模型的求解算法。算例表明本文算法所得Pareto解集优于经典的NSGA-Ⅱ算法。     

功率控制单元板卡布局优化设计研究

功率控制单元是智能配电系统中的关键单元,如何优化功率控制单元板卡的布局,从而保证其稳健的工作是工程应用中关心的重要问题.以功率控制单元为研究对象,依据该单元的设计要求,提出了功率控制单元板卡的优化设计方法.并运用Matlab软件及Lingo软件,以各板卡的功率均匀为优化目标,对具体的功率控制单元中各个板卡上配电通道的布局进行了优化设计,给出了具体的设计方案,从而使板卡的布局更加合理.     

Flying-V型仓储布局货位分配优化方法研究

Flying-V是一种典型的非传统布局方式,根据其布局方式的特性,针对仓储货位分配优化问题,以货物出入库效率最高和货物存放的重心最低为优化目标,建立了货位分配多目标优化模型,并采用自适应策略的遗传算法(GA),以及粒子群算法(PSO)进行求解。根据货位分配的优化特点,在GA算法的选择、交叉和变异环节均采用自适应策略, 同时采用惯性权重线性递减的方法设计了PSO算法,有效地解决了两种算法收敛速度慢和易“早熟”的问题,提高了算法的寻优性能。为了更好地表现两种优化求解算法的有效性和优越性,结合具体的货位分配实例利用MATLAB软件编程实现。通过对比分析优化结果表明,PSO算法在收敛速度和优化效果方面相比于自适应GA算法更具有优势,更加合适于解决Flying-V型仓储布局货位分配优化问题。     

带性能约束的矩形图元布局优化模型及不干涉性算法

本文讨论了以航天卫星仪器舱布局优化设计为背景的、带性能约束的矩形图元布局优化模型及不干涉性判别算法,主要讨论了模型的性质,并将这一模型转化为带反凸约束的凸规划问题。应用文献(4)给出的最优性条件及定界锥分拆算法,可求得带性能约束的矩形图元布局优化问题的全局最优解。     

具有动应力、位移和稳定性约束的离散变量桁架结构布局优化设计算法

给出了在动应力、动位移和动稳定约束下离散变量结构布局优化设计问题的数学模型,用“拟静力”算法,将具有动应力约束、动位移约束和动稳定约束的离散变量结构布局优化设计问题化为静应力、静位移和静稳定约束的优化问题,然后利用两级优化算法求解该模型．优化过程由两级组成,拓扑级优化和形状级优化．在每一级,都使用了综合算法,并且在搜索过程中都根据两类设计变量的相对差商值进行搜索．对包含稳定约束和不包含稳定约束的优化结果做了比较,结果显示稳定性约束对优化结果产生较大的影响．     

主通道位置不固定的设施布局问题多目标优化模型及算法

以物流中心设施布局问题为对象,提出了考虑出入口及主通道位置不固定情况下的设施布局问题的多目标优化模型并设计了其改进的遗传算法。首先,以物料搬运成本最小、活动关系密切度最大和面积利用率最大为目标,构建了考虑出入口位置不固定条件下的具有I型主通道的设施布局多目标优化数学模型。然后,设计了一种改进的遗传算法,包括:改进的编码、解码方法,追加了解码修正操作,基于惩罚函数策略的适应度函数等。实例测试表明,本算法的执行效率高而且结果稳定,优化效果好,布局结果紧凑适用。     

零售业连锁网点选址与布局演化模型

蚁群算法是近年来出现的一种新型仿生优化算法,是求解复杂优化问题有效方法.本文建立了基于蚁群算法的零售业连锁网点选址与布局演化模型,并利用Matlab进行仿真研究.通过对模拟结果的分析,验证了零售业连锁网点的选址与布局规律.     

基于改进遗传算法的布局优化子问题

本针对子问题，构造了布局子问题(关于同构布局等价类)的改进遗传算法。将该算法应用于二维布局优化子问题，数值实验表明该算法能够在很好地保持图元的邻接关系的前提下找到子问题的最优解。由于布局优化问题可分解为有限个子问题，所以利用该算法可以找到整个布局优化问题的全局最优解。     

基于改进粒子群算法V型非传统布局仓库通道优化设计

V型仓储布局是一种典型的非传统布局方式,针对V型布局主通道设计的问题,将主通道抽象为若干个点连接而成的折线通道,每条拣货通道按物动量大小对仓库进行分区,采用更加符合实际的存取货物作业的概率不相等的非完全随机存储策略,建立最小化平均拣货距离的仓库主通道设计数学优化模型。其次,设计了基于极值扰动算子的改进粒子群优化算法(EDO-PSO)进行算法求解,利用极值扰动算子解决易陷入局部最优问题,采用并行深度搜索策略,提高算法性能,并用Benchmark函数与其他改进PSO算法对比验证算法性能。最后,结合具体实验数据仿真分析,计算结果表明,该方法在相同货位分配策略下,能有效缩短总拣货距离,验证了方法的有效性。     

不确定条件下的乡村中小学布局优化

学校的合理规划布局是实现教育资源优化配置、提高办学效益和推动教育均衡发展的重要途径。已有许多学者研究了学校的布局问题,但基本上都忽略了交通网络条件以及不确定因素对学校布局的影响。本研究将在前人研究基础上,重点考虑交通网络对乡村中小学选址的影响,并假设旅行时间具有不确定性,从而以最小化学生旅行成本、学校建设、道路修建和道路升级成本为目标,构建不确定条件下的设施区位设计模型。在算法求解方面提出混合模拟退火算法,用于确定新建学校的最佳位置,以及新道路的修建和原有道路的升级情况。最后,将提出的模型和算法应用到实际案例中。     

On Using Tabu Search for Design Automation of VLSI Systems

Tabu search is a meta-heuristic problem solving technique that, when applied carefully, provides near optimal solutions in a very short time. In this paper, we have described the use of tabu search for solving problems related to very large scale integrated (VLSI) circuit design automation. Specifically, we have demonstrated the use for VLSI circuit partitioning and placement. We present a tabu search based circuit bi-partitioning technique that partitions circuits with the goal of minimizing the size of the cutset between the partitions. Then, we use tabu search techniques along with force directed placement techniques to accomplish the physical placement of VLSI circuits on regular two-dimensional arrays with the goal of minimizing the placement time. We use empirical data from partitioning and placement of benchmark circuits to test our techniques. Our methods show improvement when compared to partitioning techniques from the literature and commercially available placement tools. Relative to the literature, our tabu search bi-partitioning technique improves on the best known minimum cuts for several benchmark circuits. Relative to commercially available computer aided design tools, our tabu search based placement approach shows dramatic (20×) speedup in execution time without negative impact on the quality of the solution.     

Guided Local Search for Final Placement in VLSI Design

The design of a VLSI circuit consists of two main parts: First, the logical functionality of the circuit is described, and then the physical layout of the modules and connections is settled. In the latter process one wishes to place the modules such that the necessary wiring becomes as small as possible in order to minimize area usage and delays on signal paths. The placement problem is the subproblem of the layout problem which considers the geometric locations of the modules. A new heuristic is presented for the general cell placement problem where the objective is to minimize total bounding box netlength. The heuristic is based on the Guided Local Search (GLS) metaheuristic. GLS modifies the objective function in a constructive way to escape local minima. Previous attempts to use local search on final (or detailed) placement problems have often failed as the neighbourhood quickly becomes too excessive for large circuits. Nevertheless, by combining GLS with Fast Local Search it is possible to focus the search on appropriate sub-neighbourhoods, thus reducing the time complexity considerably. Comprehensive computational experiments with the developed algorithm are reported on a broad range of industrial circuits. The experiments demonstrate that the developed algorithm is able to improve the estimated routing length of large-sized layouts with as much as 20 percent when compared to existing algorithms.     

Efficient preprocessing for VLSI optimization problems

Advances in technology for the manufacturing of integrated circuits have resulted in extremely large, and time consuming, problems on how to lay out components for optimal circuit performance. These problems can be written as mixed integer programs which are easily relaxed to linear programs with a very high number of variables and constraints. The relaxed programs can often be solved by applying state-of-the-art linear programming software, however these solutions come at the expense of long solution time. In this paper we show that, by considering the structure inherent in VLSI problems, one can specialize classical preprocessing algorithms to take into account the standard form of the constraint matrix for VLSI problems, thereby achieving improved preprocessing results with relatively little effort. We provide analysis showing our preprocessing techniques are accurate and provide some numerical testing demonstrating the increased efficiency. The numerical tests also demonstrate that using our preprocessing in conjunction with internal preprocessing methods that come with many linear program solvers, can improve the overall performance of the linear program solver and its preprocessor.     

Integral global minimization: Algorithms,implementations and numerical tests

The theoretical foundation of integral global optimization has become widely known and well accepted [4],[24],[25]. However, more effort is needed to demonstrate the effectiveness of the integral global optimization algorithms. In this work we detail the implementation of the integral global minimization algorithms. We describe how the integral global optimization method handles nonconvex unconstrained or box constrained, constrained or discrete minimization problems. We illustrate the flexibility and the efficiency of integral global optimization method by presenting the performance of algorithms on a collection of well known test problems in global optimization literature. We provide the software which solves these test problems and other minimization problems. The performance of the computations demonstrates that the integral global algorithms are not only extremely flexible and reliable but also very efficient.Research supported partially by NSERC grant and Mount St Vincent University research grant.     

A graph partitioning heuristic for the parallel pseudo-exhaustive logical test of VLSI combinational circuits

The logical test of integrated VLSI circuits is one of the main phases of their design and fabrication. The pseudo-exhaustive approach for the logical test of integrated circults consists in partitioning the original circuits to be tested into non-overlapping subcircuits with a small, bounded number of subcircuits, which are then exhaustively tested in parallel. In this work, we present an approximate algorithm for the problem of partitioning integrated combinational circuits, based on the tabu search metaheuristic. The proposed algorithm presents several original features, such as: the use of a reduced neighborhood, obtained from moves involving only a subset of boundary nodes; complex moves which entail several resulting moves, although the variations in the cost function are easily computable; a bi-criteria cost function combining the number of subcircuits and the number of cuts, which simultaneously adds a diversification strategy to the search; and the use of a bin-packing heuristic as a post-optimization step. The behavior of the proposed algorithm was evaluated through its application to a set of benchmark circuits. The computational results have been compared with those obtained by the other algorithms in the literature, with significant improvements. The average reduction rates have been of the order of 30% in the number of subcircuits in the partition, and of the order of 40% in the number of cuts.     

An ILP based hierarchical global routing approach for VLSI ASIC design

The use of integrated circuits in high-performance computing, telecommunications, and consumer electronics has been growing at a very fast pace. The level of integration as measured by the number of logic gates in a chip has been steadily rising due to the rapid progress in processing and interconnect technology. The interconnect delay in VLSI circuits has become a critical determiner of circuit performance. As a result, circuit layout is starting to play a more important role in today’s chip designs. Global routing is one of the key sub-problems of circuit layout which involves finding an approximate path for the wires connecting the elements of the circuit without violating resource constraints. In this paper, several integer programming (ILP) based global routing models are fully investigated and explored. The resulting ILP problem is relaxed and solved as a linear programming (LP) problem followed by a rounding heuristic to obtain an integer solution. Experimental results obtained show that the proposed combined WVEM (wirelength, via, edge capacity) model can optimize several global routing objectives simultaneously and effectively. In addition, several hierarchical methods are combined with the proposed flat ILP based global router to reduce the CPU time by about 66% on average for edge capacity model (ECM).     

Quadratic 0/1 optimization and a decomposition approach for the placement of electronic circuits

The placement problem in the layout design of electronic circuits consists of finding a nonoverlapping assignment of rectangular cells to positions on the chip so that wireability is guaranteed and certain technical constraints are met. This problem can be modelled as a quadratic 0/1-program subject to linear constraints. We will present a decomposition approach to the placement problem and give results above NP-hardness and the existence of-approximative algorithms for the involved optimization problems. A graph theoretic formulation of these problems will enable us to develop approximative algorithms. Finally we will present details of the implementation of our approach and compare it to industrial state of the art placement routines.     

A survey of simulated annealing as a tool for single and multiobjective optimization

This paper presents a comprehensive review of simulated annealing (SA)-based optimization algorithms. SA-based algorithms solve single and multiobjective optimization problems, where a desired global minimum/maximum is hidden among many local minima/maxima. Three single objective optimization algorithms (SA, SA with tabu search and CSA) and five multiobjective optimization algorithms (SMOSA, UMOSA, PSA, WDMOSA and PDMOSA) based on SA have been presented. The algorithms are briefly discussed and are compared. The key step of SA is probability calculation, which involves building the annealing schedule. Annealing schedule is discussed briefly. Computational results and suggestions to improve the performance of SA-based multiobjective algorithms are presented. Finally, future research in the area of SA is suggested.     

Hybridizing local search algorithms for global optimization

In this paper, we combine two types of local search algorithms for global optimization of continuous functions. In the literature, most of the hybrid algorithms are produced by combination of a global optimization algorithm with a local search algorithm and the local search is used to improve the solution quality, not to explore the search space to find independently the global optimum. The focus of this research is on some simple and efficient hybrid algorithms by combining the Nelder–Mead simplex (NM) variants and the bidirectional random optimization (BRO) methods for optimization of continuous functions. The NM explores the whole search space to find some promising areas and then the BRO local search is entered to exploit optimal solution as accurately as possible. Also a new strategy for shrinkage stage borrowed from differential evolution (DE) is incorporated in the NM variants. To examine the efficiency of proposed algorithms, those are evaluated by 25 benchmark functions designed for the special session on real-parameter optimization of CEC2005. A comparison study between the hybrid algorithms and some DE algorithms and non-parametric analysis of obtained results demonstrate that the proposed algorithms outperform most of other algorithms and their difference in most cases is statistically considerable. In a later part of the comparative experiments, a comparison of the proposed algorithms with some other evolutionary algorithms reported in the CEC2005 confirms a better performance of our proposed algorithms.     

Chaos-enhanced accelerated particle swarm optimization

There are more than two dozen variants of particle swarm optimization (PSO) algorithms in the literature. Recently, a new variant, called accelerated PSO (APSO), shows some extra advantages in convergence for global search. In the present study, we will introduce chaos into the APSO in order to further enhance its global search ability. Firstly, detailed studies are carried out on benchmark problems with twelve different chaotic maps to find out the most efficient one. Then the chaotic APSO (CAPSO) will be compared with some other chaotic PSO algorithms presented in the literature. The performance of the CAPSO algorithm is also validated using three engineering problems. The results show that the CAPSO with an appropriate chaotic map can clearly outperform standard APSO, with very good performance in comparison with other algorithms and in application to a complex problem.