新型槽栅nMOSFET凹槽拐角效应的模拟研究

应用二维器件仿真程序PISCES Ⅱ，模拟计算了新型槽栅结构器件中凹槽拐角效应的影响与作用，讨论了槽栅结构MOSFET的沟道电场特征及其对热载流子效应、阈值电压特性等的影响.槽栅结构的凹槽拐角效应对抑制短沟道效应和抗热载流子效应是十分有利的，并且拐角结构在45°左右时拐角效应最大.调节拐角与其他结构参数，器件的热载流子效应、阈值电压特性、亚阈值特性、输出特性等都会有较大的变化. 关键词： 槽栅MOSFET 拐角效应 阈值电压 热载流子退化     

三材料线性掺杂石墨烯纳米条带场效应管性能

采用量子动力学模型研究单材料和三材料的石墨烯纳米条带场效应管(GNRFETs)在不同掺杂情况下的弹道输运特性,模型基于非平衡格林函数方程(NEGF)以及自洽的泊松方程的量子数值解.结果证明:三材料线性掺杂的石墨烯纳米条带场效应管(TL-GNRFET)不仅能够有效地抑制短沟道效应(SCE)和漏极势垒降低效应(DIBL),而且相对于其它几种结构而言,它有更好的亚阈值斜率以及更高的开关电流比.另外,还研究了非对称栅结构对石墨烯场效应管的影响,结果表明,当上栅和下栅同时向源端移动的时候,可以改善器件的电流开关比.     

非对称Halo异质栅应变Si SOI MOSFET的二维解析模型

为了进一步提高深亚微米SOI (Silicon-On-Insulator) MOSFET (Metal-Oxide Semiconductor Field Effect Transistor) 的电流驱动能力, 抑制短沟道效应和漏致势垒降低效应, 提出了非对称Halo异质栅应变Si SOI MOSFET. 在沟道源端一侧引入高掺杂Halo结构, 栅极由不同功函数的两种材料组成. 考虑新器件结构特点和应变的影响, 修正了平带电压和内建电势. 为新结构器件建立了全耗尽条件下的表面势和阈值电压二维解析模型. 模型详细分析了应变对表面势、表面场强、阈值电压的影响, 考虑了金属栅长度及功函数差变化的影响. 研究结果表明,提出的新器件结构能进一步提高电流驱动能力, 抑制短沟道效应和抑制漏致势垒降低效应, 为新器件物理参数设计提供了重要参考. 关键词： 非对称Halo 异质栅 应变Si 短沟道效应     

高k介质异质栅全耗尽SOI MOSFET二维解析模型

为了研究高介电常数(高k)栅介质材料异质栅中绝缘衬底上的硅和金属-氧化物-硅场效应晶体管的短沟道效应,为新结构器件建立了全耗尽条件下表面势和阈值电压的二维解析模型.模型中考虑了各种主要因素的影响,包括不同介电常数材料的影响,栅金属长度及其功函数变化的影响,不同漏电压对短沟道效应的影响.结果表明,沟道表面势中引入了阶梯分布,因此源端电场较强;同时漏电压引起的电势变化可以被屏蔽,抑制短沟道效应.栅介电常数增大,也可以较好的抑制短沟道效应.解析模型与数值模拟软件ISE所得结果高度吻合. 关键词： 异质栅 绝缘衬底上的硅 阈值电压 解析模型     

异质栅全耗尽应变硅金属氧化物半导体模型化研究

为了进一步提高小尺寸金属氧化物半导体(MOSFET)的性能,在应变硅器件的基础上, 提出了一种新型的异质栅MOSFET器件结构.通过求解二维Poisson方程,结合应变硅技术的物理原理,建立了表面势、表面电场以及阈值电压的物理模型,研究了栅金属长度、功函数以及双轴应变对其的影响. 通过仿真软件ISE TCAD进行模拟仿真,模型计算与数值模拟的结果基本符合. 研究表明：与传统器件相比,本文提出的异质栅应变硅新器件结构的载流子输运效率进一步提高, 可以很好地抑制小尺寸器件的短沟道效应、漏极感应势垒降低效应和热载流子效应, 使器件性能得到了很大的提升. 关键词： 应变硅 异质栅 阈值电压 解析模型     

对称三材料双栅应变硅金属氧化物半导体场效应晶体管二维解析模型

提出了对称三材料双栅应变硅金属氧化物半导体场效应晶体管器件结构,为该器件结构建立了全耗尽条件下的表面势模型、表面场强和阈值电压解析模型,并分析了应变对表面势、表面场强和阈值电压的影响,讨论了三栅长度比率对阈值电压和漏致势垒降低效应的影响,对该结构器件与单材料双栅结构器件的性能进行了对比研究.结果表明,该结构能进一步提高载流子的输运速率,更好地抑制漏致势垒降低效应.适当优化三材料栅的栅长比率,可以增强器件对短沟道效应和漏致势垒降低效应的抑制能力.     

高κ介质异质栅全耗尽SOI MOSFET二维解析模型

为了研究高介电常数(高κ)栅介质材料异质栅中绝缘衬底上的硅和金属-氧化物-硅场效应晶体管的短沟道效应,为新结构器件建立了全耗尽条件下表面势和阈值电压的二维解析模型.模型中考虑了各种主要因素的影响,包括不同介电常数材料的J影响,栅金属长度及其功函数变化的影响,不同漏电压对短沟道效应的影响.结果表明,沟道表面势中引入了阶梯分布,因此源端电场较强;同时漏电压引起的电势变化可以被屏蔽,抑制短沟道效应.栅介电常数增大,也可以较好的抑制短沟道效应.解析模型与数值模拟软件ISE所得结果高度吻合.     

堆叠栅介质对称双栅单Halo应变Si金属氧化物半导体场效应管二维模型

提出了一种堆叠栅介质对称双栅单Halo应变Si金属氧化物半导体场效应管(metal-oxide semiconductor field effect transistor,MOSFET)新器件结构.采用分区的抛物线电势近似法和通用边界条件求解二维泊松方程,建立了全耗尽条件下的表面势和阈值电压的解析模型.该结构的应变硅沟道有两个掺杂区域,和常规双栅器件(均匀掺杂沟道)比较,沟道表面势呈阶梯电势分布,能进一步提高载流子迁移率;探讨了漏源电压对短沟道效应的影响;分析得到阈值电压随缓冲层Ge组分的提高而降低,随堆叠栅介质高k层介电常数的增大而增大,随源端应变硅沟道掺杂浓度的升高而增大,并解释了其物理机理.分析结果表明:该新结构器件能够更好地减小阈值电压漂移,抑制短沟道效应,为纳米领域MOSFET器件设计提供了指导.     

单Halo全耗尽应变Si 绝缘硅金属氧化物半导体场效应管的阈值电压解析模型

为了改善金属氧化物半导体场效应管(MOSFET) 的短沟道效应(SCE)、 漏致势垒降低(DIBL) 效应, 提高电流的驱动能力, 提出了单Halo 全耗尽应变硅绝缘体 (SOI) MOSFET 结构, 该结构结合了应变Si, 峰值掺杂Halo结构, SOI 三者的优点. 通过求解二维泊松方程, 建立了全耗尽器件表面势和阈值电压的解析模型. 模型中分析了弛豫层中的Ge组分对表面势、表面场强和阈值电压的影响, 不同漏电压对表面势的影响, Halo 掺杂对阈值电压和DIBL的影响.结果表明, 该新结构能够抑制SCE和DIBL效应, 提高载流子的输运效率. 关键词： 应变Si 阈值电压 短沟道效应 漏致势垒降低     

基于非平衡Green函数理论的峰值掺杂-低掺杂漏结构碳纳米管场效应晶体管输运研究

为改善碳纳米管场效应晶体管的性能,将一种峰值掺杂-低掺杂漏(HALO-LDD)掺杂结构引入碳纳米管沟道.在量子力学非平衡Green函数理论框架内,通过自洽求解Poisson方程和Schrödinger方程,构建了适用于非均匀掺杂的碳纳米管场效应管的输运模型,该模型可实现场效应晶体管的输运性质与碳纳米管手性指数的对接. 利用该模型研究了单HALO双LDD 掺杂结构对碳纳米管场效应晶体管输运特性的影响.对比分析表明,这种非均匀掺杂结构的场效应管同本征碳纳米管沟道场效应晶体管相比,具有更低的泄漏电流、更大的电流开关比、更小的亚阈区栅电压摆幅,表明其具有更好的栅控能力; 具有更小的漏源电导,更适合应用于模拟集成电路中;具有更小的阈值电压漂移,表明更能抑制短沟道效应. 同本征沟道碳纳米管场效应晶体管相比,这种非均匀掺杂碳纳米管场效应晶体管在沟道区靠近源端位置,电场强度增大, 有利于增大电子的传输速率;在沟道区靠近漏端位置,电场强度减小,更有利于抑制热电子效应.     

The effects of source/drain and gate overlap on the performance of carbon nanotube field effect transistors

At nanometer regime, fabricating the structures with non-overlapped channel and abrupt doping profile is very complicated and sometimes impossible. So, the resultant device experiences some non-ideal effects which have to be predicted and well addressed by simulation before fabrication. In this paper the effects of overlap between gate and source/drain regions on the performance of carbon nanotube field effect transistors have been investigated. The overlapped structure has been simulated with various doping profiles at drain/source and gate region junction tip. The device performance has been investigated in terms of ON current, Off current, ON/Off current ratio, subthreshold swing, delay, and power delay product (PDP). Simulations show that depending on the variations in the effective channel length, the overlap deteriorates some device characteristics and enhances the others. Where the effective channel length decreases (increases), the overlap deteriorates (enhances) the current ratio and subthreshold swing but enhances (deteriorates) the delay and PDP compared to non-overlapped structure. Furthermore, the overlapped structure with graded profile results in lower current ratio and higher subthreshold swing compared to overlapped structure with abrupt profile. At a fixed current ratio, the delay and PDP of overlapped structure with graded profile are more than overlapped structure with abrupt profile but at a fixed channel length, both profiles have approximately equal delay and PDP.     

Analytical model including the fringing-induced barrier lowering effect for a dual-material surrounding-gate MOSFET with a high-κ gate dielectric

By solving Poisson’s equation in both semiconductor and gate insulator regions in the cylindrical coordinates, an analytical model for a dual-material surrounding-gate (DMSG) metal–oxide semiconductor field-effect transistor (MOSFET) with a high-κ gate dielectric has been developed. Using the derived model, the influences of fringing-induced barrier lowering (FIBL) on surface potential, subthreshold current, DIBL, and subthreshold swing are investigated. It is found that for the same equivalent oxide thickness, the gate insulator with high-κ dielectric degrades the short-channel performance of the DMSG MOSFET. The accuracy of the analytical model is verified by the good agreement of its results with that obtained from the ISE three-dimensional numerical device simulator.     

Analytical model including the fringing-induced barrier lowering effect for a dual-material surrounding-gate MOSFET with a high-kappa gate dielectric

By solving Poisson's equation in both semiconductor and gate insulator regions in the cylindrical coordinates, an analytical model for a dual-material surrounding-gate (DMSG) metal-oxide semiconductor field-effect transistor (MOSFET) with a high-kappa gate dielectric has been developed. Using the derived model, the influences of fringing-induced barrier lowering (FIBL) on surface potential, subthreshold current, DIBL, and subthreshold swing are investigated. It is found that for the same equivalent oxide thickness, the gate insulator with high-kappa dielectric degrades the short-channel performance of the DMSG MOSFET. The accuracy of the analytical model is verified by the good agreement of its results with that obtained from the ISE three-dimensional numerical device simulator.     

A two-dimensional analytical analysis of subthreshold behavior to study the scaling capability of nanoscale graded channel gate stack DG MOSFETs

In this paper, a new nanoscale graded channel gate stack (GCGS) double-gate (DG) MOSFET structure and its 2-D analytical model have been proposed, investigated and expected to suppress the short-channel-effects (SCEs) and improve the subthreshold performances for nanoelectronics applications. The model predicts a shift, increasing potential barrier, in the surface potential profile along the channel, which ensures a reduced threshold voltage roll-off and DIBL effects. In the proposed structure, the subthreshold current and subthreshold swing characteristics are greatly improved in comparison with the conventional DG MOSFETs. The developed approaches are verified and validated by the good agreement found with the numerical simulation. (GCGS) DG MOSFET can alleviate the critical problem and further improve the immunity of SCEs of CMOS-based devices in the nanoscale regime.     

An optimized design of 10-nm-scale dual-material surrounded gate MOSFETs for digital circuit applications

In this paper, we have proposed and simulated a new 10-nm Dual-Material Surrounded Gate MOSFETs (DMSG) MOSFETs for nanoscale digital circuit applications. The subthreshold electrical properties such as subthreshold current–voltage characteristics, subthreshold swing factor, threshold voltage and drain induced barrier lowering (DIBL) of the device have been ascertained and mathematical models have been developed. It has been observed that the DM design can effectively suppress short-channel effects as compared to single material gate structure. The proposed analytical expressions are used to formulate the objective functions, which are the pre-requisite of genetic algorithm computation. The problem is then presented as a multi-objective optimization one where the subthreshold electrical parameters are considered simultaneously. Therefore, the proposed technique is used to search of the optimal electrical and geometrical parameters to obtain better electrical performance of the 10-nm-scale transistor. These characteristics make the optimized 10-nm transistors potentially suitable for deep nanoscale logic and memory applications.     

Study on two-dimensional analytical models for symmetrical gate stack dual gate strained silicon MOSFETs

Based on the exact resultant solution of two-dimensional Poisson’s equation, the novel two-dimensional models, which include surface potential, threshold voltage, subthreshold current and subthreshold swing, have been developed for gate stack symmetrical double-gate strained-Si MOSFETs. The models are verified by numerical simulation. Besides offering the physical insight into device physics, the model provides the basic designing guidance of further immunity of short channel effect of complementary metal-oxide-semiconductor (CMOS)-based device in a nanoscale regime.     

The study on two-dimensional analytical model for gate stack fully depleted strained Si on silicon-germanium-on-insulator MOSFETs

Based on the exact resultant solution of two-dimensional Poisson's equation in strained Si and Si_{1 - X}Ge_X layer, a simple and accurate two-dimensional analytical model including surface channel potential, surface channel electric field, threshold voltage and subthreshold swing for fully depleted gate stack strained Si on silicon-germanium-on-insulator (SGOI) MOSFETs has been developed. The results show that this novel structure can suppress the short channel effects (SCE), the drain-induced barrier-lowering (DIBL) and improve the subthreshold performance in nanoelectronics application. The model is verified by numerical simulation. The model provides the basic designing guidance of gate stack strained Si on SGOI MOSFETs.     

Analytical modeling of subthreshold current and subthreshold swing of short-channel triple-material double-gate (TM-DG) MOSFETs

An analytical model for subthreshold current and subthreshold swing of short-channel triple-material double-gate (TM-DG) MOSFETs is presented in this paper. Both the drift and diffusion components of current densities are considered for the modeling of subthreshold current. Virtual cathode concept of DG MOSFETs is utilized to model the subthreshold swing of TM-DG MOSFETs. The effect of different length ratios of the three channel regions under three different gate materials of device on the subthreshold current and subthreshold swing of the short-channel TM-DG MOSFETs have been discussed. The dependencies of subthreshold current and subthreshold swing on various device parameters have been studied. The simulation data obtained by using the commercially available 2D device simulation software ATLAS™ has been used to validate the present model.     

A two-dimensional analytical subthreshold behavior model for junctionless dual-material cylindrical surrounding-gate MOSFETs

A two-dimensional analytical subthreshold behavior model for junctionless dual-material cylindrical surrounding- gate （JLDMCSG） metal-oxide-semiconductor field-effect transistors （MOSFETs） is proposed. It is derived by solving the two-dimensional Poisson＇s equation in two continuous cylindrical regions with any simplifying assumption. Using this analytical model, the subthreshold characteristics of JLDMCSG MOSFETs are investigated in terms of channel electro- static potential, horizontal electric field, and subthreshold current. Compared to junctionless single-material cylindrical surrounding-gate MOSFETs, JLDMCSG MOSFETs can effectively suppress short-channel effects and simultaneously im- prove carrier transport efficiency. It is found that the subthreshold current of JLDMCSG MOSFETs can be significantly reduced by adopting both a thin oxide and thin silicon channel. The accuracy of the analytical model is verified by its good agreement with the three-dimensional numerical simulator ISE TCAD.     

Two-dimensional analytical subthreshold model of graded channel DG FD SOI n-MOSFET with gate misalignment effect

A two-dimensional (2-D) analytical subthreshold model is developed for a graded channel double gate (DG) fully depleted SOI n-MOSFET incorporating a gate misalignment effect. The conformal mapping transformation (CMT) approach has been used to provide an accurate prediction of the surface potential, electric field, threshold voltage and subthreshold behavior of the device, considering the gate misalignment effect to be on both source and drain side. The model is applied to both uniformly doped (UD) and graded channel (GC) DG MOSFETs. The results of an analytical model agree well with 3-D simulated data obtained by ATLAS-3D device simulation software.