Analytical threshold voltage model for strained silicon GAA-TFET

Tunnel field effect transistors(TFETs) are promising devices for low power applications.An analytical threshold voltage model,based on the channel surface potential and electric field obtained by solving the 2D Poisson's equation,for strained silicon gate all around TFETs is proposed.The variation of the threshold voltage with device parameters,such as the strain(Ge mole fraction x),gate oxide thickness,gate oxide permittivity,and channel length has also been investigated.The threshold voltage model is extracted using the peak transconductance method and is verified by good agreement with the results obtained from the TCAD simulation.     

Effect of channel thickness on electrical performance of amorphous IGZO thin-film transistor with atomic layer deposited alumina oxide dielectric

We have investigated the electrical performance of amorphous indium–gallium–zinc oxide (α-IGZO) thin-film transistors with various channel thicknesses. It is observed that when the α-IGZO thickness increases, the threshold voltage decreases as reported at other researches. The intrinsic field-effect mobility as high as 11.1 cm²/Vs and sub threshold slope as low as ∼0.2 V/decade are independent on the thickness of α-IGZO channel, which indicate the excellent interface between α-IGZO and atomic layer deposited Al₂O₃ dielectric even for the case with α-IGZO thickness as thin as 10 nm. However, the source and drain series resistances increased with increasing of α-IGZO channel thickness, which results in the apparent field-effect mobility decreasing. The threshold voltage shift (ΔV_th) under negative bias stress (NBS) and negative bias illumination stress (NBIS) were investigated, also. The hump-effect in the sub threshold region under NBS and threshold voltage shift to negative position under NBIS were enhanced with decreasing of α-IGZO channel thickness, owing to the enhancement of vertical electrical field in channel.     

Monte Carlo particle-based simulations of deep-submicron n-MOSFETs with real-space treatment of electron–electron and electron–impurity interactions

In modern deep-submicron devices, for achieving optimum device performance, the doping densities must be quite high. This necessitates a careful treatment of the short- and long-range electron–electron and electron–impurity interactions. We have shown before that by using a corrected Coulomb force, in conjunction with a proper cutoff range, one can properly account for the short-range portion of the force. Our approach naturally incorporates multi-ion contributions, local distortions in the scattering potential due to the movement of the free charges, and carrier-density fluctuations. The doping dependence of the low-field electron mobility obtained from 3D resistor simulations closely followed the experimental results, thus proving the correctness of our approach. Here, we discuss how discrete impurity effects affect the threshold voltage of ultra-small n-channel MOSFETs with gate lengths ranging from 50 to 100 nm. We find that the fluctuations in the threshold voltage increase with increasing the oxide thickness and substrate doping. The averaging effect over the width of the device leads to significantly smaller fluctuations in the threshold voltage for devices with larger gate width. The observed trends are in agreement with the experimental findings.     

Shrinking limits of silicon MOSFETs: numerical study of 10 nm scale devices

We have performed numerical modeling of dual-gate ballistic n-MOSFETs with channel length of the order of 10 nm, including the effects of quantum tunneling along the channel and through the gate oxide. Our analysis includes a self-consistent solution of the full (two-dimensional) electrostatic problem, with account of electric field penetration into the heavily doped electrodes. The results show that transistors with channel length as small as 8 nm can exhibit either a transconductance up to 4000 mS mm ^− 1or gate modulation of current by more than 8 orders of magnitude, depending on the gate oxide thickness. These characteristics make the devices satisfactory for logic and memory applications, respectively, although their gate threshold voltage is rather sensitive to nanometer-scale variations in the channel length.     

MOSFET scaling into the 10 nm regime

Scaling limits of the double-gate MOSFET structure are explored. Because short-channel effects can be adequately controlled by thinning the silicon body, the eventual scaling limit will be determined by the ability to control off-state leakage due to quantum mechanical tunneling and thermionic emission between the source and drain. Depending on threshold voltage and the source/drain doping profile, this will restrict gate length scaling to 5–11 nm. As power supplies are scaled down, maintaining on-state drive current may become difficult due to threshold voltage limitations. Series resistance becomes important as the body thickness is reduced, but intrinsic device performance may still be improved.     

Effects of imperfect premixing coupled with hydrodynamic instability on flame propagation

The problem of flame propagation in imperfectly premixed mixtures—mixtures of reactants with variable composition—is considered in this numerical study. We carry out two-dimensional direct numerical simulations of a flame propagating in a globally lean fuel-oxidizer mixture with imposed velocity and composition fluctuations of various intensities. The configuration adopted is that of a flame front interacting with spatially evolving fluctuations, and the characteristic scales of the domain and of the fluctuations imposed are significantly larger than the characteristic thickness of the flame, to account for important flame dynamics such as the hydrodynamic instability. One-step chemistry and Fick’s diffusion law are considered, along with unity Lewis number assumption for all the species. It is observed, in agreement with previous results, that relatively weak fluctuations in composition alone may lead to a large increase in flame length and burning rate. The hydrodynamic instability caused by gas expansion, catalyzed by the composition fluctuations interacting with the flame, is found to be responsible for the flame length enhancement. It is observed as well that the relative importance of this effect diminishes as the velocity fluctuations present become more intense, and that composition fluctuations have a small impact on flame length for these cases. It is additionally found that, with increasing intensity of composition fluctuations, there is eventually a reduction of burning rate per unit length of flame which leads, consequently, to a weak reduction of overall burning rate for the largest velocity fluctuation intensities covered by this study.     

Structural characterization of Mg substituted on A/B sites in $$\hbox {NiFe}_2\hbox {O}_4$$ nanoparticles using autocombustion method

A compact quantitative model based on oxide semiconductor interface density of states (DOS) is proposed for Al_0.25Ga_0.75N/GaN metal oxide semiconductor high electron mobility transistor (MOSHEMT). Mathematical expressions for surface potential, sheet charge concentration, gate capacitance and threshold voltage have been derived. The gate capacitance behaviour is studied in terms of capacitance–voltage (CV) characteristics. Similarly, the predicted threshold voltage (V _T) is analysed by varying barrier thickness and oxide thickness. The positive V _T obtained for a very thin 3 nm AlGaN barrier layer enables the enhancement mode operation of the MOSHEMT. These devices, along with depletion mode devices, are basic constituents of cascode configuration in power electronic circuits. The expressions developed are used in conventional long-channel HEMT drain current equation and evaluated to obtain different DC characteristics. The obtained results are compared with experimental data taken from literature which show good agreement and hence endorse the proposed model.     

Influence of the thickness of the tunnel layer on the charging characteristics of Si nanocrystals embedded in an ultra-thin SiO2 layer

In this paper, we have studied the effect of the thickness of the initial SiO₂ layer (5–7 nm) on the charge and discharge properties of a 2D array of Si nanoparticles embedded in these SiO₂ layers fabricated by ultra-low-energy ion implantation (ULE-II) and annealing. The structural characteristics of these nanocrystal-based memories (position of the nanocrystals with respect to the electrodes, size and surface density of the particles in the plane) were studied by transmission electron microscopy (TEM) and energy filtered TEM (EF-TEM). Electrical characterizations were performed at room temperature using a nano-MOS capacitor to be able to address only a few nanoparticles (nps). EFTEM gives the measurements of oxide thickness, injection, control and nps distances, size and density. I–V and I–t measurements exhibit current peaks and random telegraph signal fluctuations that can be interpreted as due to quantized charging of the nps and to some electrostatic interactions between the trapped charges and the tunnelling current. We have shown that these characteristics strongly vary with the initial oxide thickness, exhibiting several charging/discharging events for the 7-nm-thick layer while charging events prevail in the case of 5-nm-thick layer. These results indicate that the probability of discharging phenomena is reduced when the tunnel layer thickness decreases.     

Quasi-two-dimensional threshold voltage model for junctionless cylindrical surrounding gate metal-oxide-semiconductor field-effect transistor with dual-material gate

Based on the quasi-two-dimensional(2D) solution of Poisson’s equation in two continuous channel regions, an analytical threshold voltage model for short-channel junctionless dual-material cylindrical surrounding-gate(JLDMCSG) metal-oxide-semiconductor field-effect transistor(MOSFET) is developed. Using the derived model, channel potential distribution, horizontal electrical field distribution, and threshold voltage roll-off of JLDMCSG MOSFET are investigated. Compared with junctionless single-material CSG(JLSGCSG) MOSFET, JLDMCSG MOSFET can effectively suppress short-channel effects and simultaneously improve carrier transport efficiency. It is also revealed that threshold voltage rolloff of JLDMCSG can be significantly reduced by adopting both a small oxide thickness and a small silicon channel radius. The model is verified by comparing its calculated results with that obtained from three-dimensional(3D) numerical device simulator ISE.     

Threshold switching uniformity in In_2Se_3 nanowire-based phase change memory

The uniformity of threshold voltage and threshold current in the In2Se3nanowire-based phase change memory(PCM)devices is investigated. Based on the trap-limited transport model, amorphous layer thickness, trap density, and trap depth are considered to clarify their influences upon the threshold voltage and threshold current through simulations.     

新型高速半导体器件IMOS阈值电压解析模型

本文在研究IMOS器件结构的基础上, 分析了该器件不同区域的表面电场, 结合雪崩击穿条件, 建立了P-IMOS的阈值电压解析模型. 应用MATLAB对该器件阈值电压模型与源漏电压、栅长和硅层厚度的关系进行了数值分析, 并用二维器件仿真工具ISE进行了验证. 结果表明, 源电压越大, 阈值电压值越小; 栅长所占比例越大, 阈值电压值越小, 硅层厚度越小, 阈值电压值越小. 本文提出的模型与ISE仿真结果一致, 也与文献报道符合. 这种新型高速半导体器件IMOS阈值电压解析模型的建立为该高性能器件及对应电路的设计、仿真和制造提供了重要的参考.     

Radiation damage effects on power VDMOS devices with composite SiO2–Si3N4 films

Total dose effects and single event effects on radiation-hardened power vertical double-diffusion metal oxide semiconductor (VDMOS) devices with composite SiO₂-–Si₃N₄ film gate are investigated. The relationships among the important electrical parameters of the samples with different thickness SiO₂-–Si₃N₄ films, such as threshold voltage, breakdown voltage, and on-state resistance in accumulated dose, are discussed. The total dose experiment results show that the breakdown voltage and the on-state resistance barely change with the accumulated dose. However, the relationships between the threshold voltages of the samples and the accumulated dose are more complex, not only positive drift, but also negative drift. At the end of the total dose experiment, we select the group of samples which have the smaller threshold voltage shift to carry out the single event effect studies. We find that the samples with appropriate thickness ratio SiO₂-–Si₃N₄ films have a good radiation-hardening ability. This method may be useful in solving both the SEGR and the total dose problems with the composite SiO₂-–Si₃N₄ films.     

Hot-carrier degradation for 90nm gate length LDD-NMOSFET with ultra-thin gate oxide under low gate voltage stress

The hot-carrier degradation for 90~nm gate length lightly-doped drain (LDD) NMOSFET with ultra-thin (1.4~nm) gate oxide under the low gate voltage (LGV) (at V_g=V_th, where V_th is the threshold voltage) stress has been investigated. It is found that the drain current decreases and the threshold voltage increases after the LGV (V_g=V_th stress. The results are opposite to the degradation phenomena of conventional NMOSFET for the case of this stress. By analysing the gate-induced drain leakage (GIDL) current before and after stresses, it is confirmed that under the LGV stress in ultra-short gate LDD-NMOSFET with ultra-thin gate oxide, the hot holes are trapped at interface in the LDD region and cannot shorten the channel to mask the influence of interface states as those in conventional NMOSFET do, which leads to the different degradation phenomena from those of the conventional NMOS devices. This paper also discusses the degradation in the 90~nm gate length LDD-NMOSFET with 1.4~nm gate oxide under the LGV stress at V_g=V_th with various drain biases. Experimental results show that the degradation slopes (n) range from 0.21 to 0.41. The value of n is less than that of conventional MOSFET (0.5-0.6) and also that of the long gate length LDD MOSFET (\sim0.8).     

Novel structure formation at the bottom surface of porous anodic alumina fabricated by single step anodization process

A simple approach for the growth of long-range highly ordered nanoporous anodic alumina film in H₂SO₄ electrolyte through a single step anodization without any additional pre-anodizing procedure is reported. Free-standing porous anodic alumina film of 180 μm thickness with through hole morphology was obtained. A simple and single step process was used for the detachment of alumina from aluminum substrate. The effect of anodizing conditions, such as anodizing voltage and time on the pore diameter and pore ordering is discussed. The metal/oxide and oxide/electrolyte interfaces were examined by high resolution scanning transmission electron microscope. The arrangement of pores on metal/oxide interface was well ordered with smaller diameters than that of the oxide/electrolyte interface. The inter-pore distance was larger in metal/oxide interface as compared to the oxide/electrolyte interface. The size of the ordered domain was found to depend strongly upon anodizing voltage and time.     

Electrical and thermal properties of Ge40S60 films

Films of the composition Ge₄₀S₆₀ have been studied in the temperature range of 313–423 K for electrical conductivity, and 293–373 K for thermal conductivity. The dc conductivity results indicate a single value activation energy of 0.863 eV for the conductivity in the applied temperature range. The thermal conductivity coefficient increases linearly with temperature at a thickness of d=0.311 cm. It was found that the investigated samples show a memory effect. The threshold switching voltage was found to increase linearly with film thickness. Moreover, the threshold voltage decreases exponentially with temperature. The data are analysed using a thermal model for the switching process.     

Statistical 3D ‘atomistic’ simulation of decanano MOSFETs

A 3D statistical ‘atomistic’ simulation technique has been developed to study the effect of the random dopant induced parameter fluctuations in aggressively scaled MOSFETs. Efficient implementation of the ‘atomistic’ simulation approach has been used to investigate the threshold voltage standard deviation and lowering in the case of uniformly doped MOSFETs, and in fluctuation-resistant architectures utilising epitaxial-layers and delta-doping. The effect of the random doping in the polysilicon gate on the threshold voltage fluctuations has also been thoroughly investigated. The influence of a single-charge trapping on the channel conductivity in decanano MOSFETs is studied in the ‘atomistic’ framework as well. Quantum effects are taken into consideration in our ‘atomistic’ simulations using the density gradient formalism.     

On the dynamics and disentanglement in thin and two-dimensional polymer films

We present results from molecular dynamics simulations of strictly two-dimensional (2D) polymer melts and thin polymer films in a slit geometry of thickness of the order of the radius of gyration. We find that the dynamics of the 2D melt is qualitatively different from that of the films. The 2D monomer mean-square displacement shows a t^8/15 power law at intermediate times instead of the t^1/2 law expected from Rouse theory for nonentangled chains. In films of finite thickness, chain entanglements may occur. The impact of confinement on the entanglement length N_e has been analyzed by a primitive path analysis. The analysis reveals that N_e increases strongly with decreasing film thickness.     

Ge组分对应变Si1-xGe x 沟道p-MOSFET电学特性影响

利用二维数值模拟方法,研究了不同Ge组分应变Si_1-xGe _x 沟道p-MOSFET的电容-电压特性以及阈值电压的变化情况.计算结果表明:提高应变Si_1-xGe _x 沟道层中的Ge组分,器件亚阈值电流明显增大;栅电容在器件进入反型状态时产生显著变化;阈值电压的改变量与Ge组分基本成线性关系.通过改变Si_1-xGe _x 沟道的长度,并结 关键词： 1-xGe _x 沟道')" href="#">应变Si_1-xGe _x 沟道 p-MOSFET 空穴迁移率 栅电容     

Investigation on threshold voltage of p-channel GaN MOSFETs based on p-GaN/AlGaN/GaN heterostructure

The threshold voltage (V_th) of the p-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) is investigated via Silvaco-Atlas simulations. The main factors which influence the threshold voltage of p-channel GaN MOSFETs are barrier height Φ_1,p, polarization charge density σ_b, and equivalent unite capacitance C_oc. It is found that the thinner thickness of p-GaN layer and oxide layer will acquire the more negative threshold voltage V_th, and threshold voltage |V_th| increases with the reduction in p-GaN doping concentration and the work-function of gate metal. Meanwhile, the increase in gate dielectric relative permittivity may cause the increase in threshold voltage |V_th|. Additionally, the parameter influencing output current most is the p-GaN doping concentration, and the maximum current density is 9.5 mA/mm with p-type doping concentration of 9.5×10¹⁶ cm^-3 at V_GS = -12 V and V_DS = -10 V.     

Physics of fluctuation processes in downscaled silicon MOSFETs

Physical mechanics of fluctuation processes in advanced submicron and decananometer MOSFETs (metal-oxide-semiconductor field-effect transistors) including the ultra-thin film SOI (siliconon-insulator) devices using strained silicon films are reviewed. The review is substantially based on the results obtained by the authors. It is shown that the following drastic changes occur in the nature and parameters of noise in such devices as a result of their downscaling when the gate oxide thickness and the channel length and width are decreased, the SOI substrates are used, the silicon film thickness is reduced, the film doping level is varied, the strained silicon films are employed, etc. Firstly, the Lorentzian components can appear in the current noise spectra. Those components are due to (i) electron tunneling from the valence band through the gate oxide in the SOI MOSFETs of a sufficiently thin gate oxide (LKE-Lorentzians); (ii) Nyquist fluctuations generated in the source and drain regions near the back Si/SiO₂ interface in the SOI MOSFETs (BGI Lorentzians); (iii) electron exchange between the channel and some single trap in the gate oxide of the transistors with sufficiently small length and width of the channel (RTS Lorentzians). Secondly, the 1/f-noise level can increase due to (i) the appearance of recombination processes near the Si/SiO₂ interface activated by the currents of electron tunneling from the valence band; (ii) an increase in the trap density in the gate oxide of the devices fabricated on the biaxially tensile-strained silicon films; (iii) the contribution of the 1/f fluctuations of the current flowing through the gate oxide as a result of electron tunneling from the conduction band. At the same time, the 1/f-noise level may decrease due to a decrease in the trap density in the gate oxide of the transistors fabricated on the uniaxially tensile-strained silicon films. Moreover, a 1/f ^1.7 component may appear in the noise spectra for the transistors of a sufficiently thin gate oxide, whose component is due to charge fluctuations on the defects located near the interface between the gate polysilicon and the gate oxide.