A threshold voltage analytical model for high-k gate dielectric MOSFETs with fully overlapped lightly doped drain structures

We investigate the influence of voltage drop across the lightly doped drain(LDD) region and the built-in potential on MOSFETs,and develop a threshold voltage model for high-k gate dielectric MOSFETs with fully overlapped LDD structures by solving the two-dimensional Poisson’s equation in the silicon and gate dielectric layers.The model can predict the fringing-induced barrier lowering effect and the short channel effect.It is also valid for non-LDD MOSFETs.Based on this model,the relationship between threshold voltage roll-off and three parameters,channel length,drain voltage and gate dielectric permittivity,is investigated.Compared with the non-LDD MOSFET,the LDD MOSFET depends slightly on channel length,drain voltage,and gate dielectric permittivity.The model is verified at the end of the paper.     

Analytical model including the fringing-induced barrier lowering effect for a dual-material surrounding-gate MOSFET with a high-k gate dielectric

By solving Poisson＇s equation in both semiconductor and gate insulator regions in the cylindrical coordinates, an analytical model for a dual-material surrounding-gate （DMSG） metal-oxide semiconductor field-effect transistor （MOSFET） with a high-k gate dielectric has been developed. Using the derived model, the influences of fringing-induced barrier lowering （FIBL） on surface potential, subthreshold current, DIBL, and subthreshold swing are investigated. It is found that for the same equivalent oxide thickness, the gate insulator with high-k dielectric degrades the short-channel performance of the DMSG MOSFET. The accuracy of the analytical model is verified by the good agreement of its results with that obtained from the ISE three-dimensional numerical device simulator.     

A novel partial silicon on insulator high voltage LDMOS with low-k dielectric buried layer

A novel partial silicon-on-insulator (PSOI) high voltage device with a low-k (relative permittivity) dielectric buried layer (LK PSOI) and its breakdown mechanism are presented and investigated by MEDICI.At a low k value the electric field strength in the dielectric buried layer (E I) is enhanced and a Si window makes the substrate share the vertical drop,resulting in a high vertical breakdown voltage;in the lateral direction,a high electric field peak is introduced at the Si window,which modulates the electric field distribution in the SOI layer;consequently,a high breakdown voltage (BV) is obtained.The values of EI and BV of LK PSOI with kI=2 on a 2 μm thick SOI layer over 1 μm thick buried layer are enhanced by 74% and 19%,respectively,compared with those of the conventional PSOI.Furthermore,the Si window also alleviates the self-heating effect.     

Compound buried layer SOI high voltage device with a step buried oxide

A silicon-on-insulator (SOI) high performance lateral double-diffusion metal oxide semiconductor (LDMOS) on a compound buried layer (CBL) with a step buried oxide (SBO CBL SOI) is proposed.The step buried oxide locates holes in the top interface of the upper buried oxide (UBO) layer.Furthermore,holes with high density are collected in the interface between the polysilicon layer and the lower buried oxide (LBO) layer.Consequently,the electric fields in both the thin LBO and the thick UBO are enhanced by these holes,leading to an improved breakdown voltage.The breakdown voltage of the SBO CBL SOI LDMOS increases to 847 V from the 477 V of a conventional SOI with the same thicknesses of SOI layer and the buried oxide layer.Moreover,SBO CBL SOI can also reduce the self-heating effect.     

考虑量子效应的高k栅介质SOIMOSFET特性研究

本文主要研究考虑量子效应的高k栅介质SOIMOSFET器件特性．通过数值方法自治求解薛定谔方程和泊松方程,得到了垂直于SiO2／Si界面方向上载流子波函数及能级的分布情况,结合Young模型,在考虑短沟道效应和高庀栅介质的情况下,对SOIMOSFET的阈值电压进行模拟分析．结果表明：随着纵向电场的增加,量子化效应致使反型层载流子分布偏离表面越来越严重,造成了有效栅氧化层厚度的增加和阈值电压波动．采用高向栅介质材料,可以减小阈值电压,抑制DIBL效应．较快的运算速度保证了模拟分析的效率,计算结果和ISE仿真结果的符合说明了本文的模型精度高．     

High-voltage super-junction lateral double-diffused metal-oxide semiconductor with a partial lightly doped pillar

A novel super-junction lateral double-diffused metal-oxide semiconductor(SJ-LDMOS) with a partial lightly doped P pillar(PD) is proposed.Firstly,the reduction in the partial P pillar charges ensures the charge balance and suppresses the substrate-assisted depletion effect.Secondly,the new electric field peak produced by the P/P-junction modulates the surface electric field distribution.Both of these result in a high breakdown voltage(BV).In addition,due to the same conduction paths,the specific on-resistance(R on,sp) of the PD SJ-LDMOS is approximately identical to the conventional SJ-LDMOS.Simulation results indicate that the average value of the surface lateral electric field of the PD SJ-LDMOS reaches 20V/μm at a 15μm drift length,resulting in a BV of 300V.     

Non-depletion floating layer in SOI LDMOS for enhancing breakdown voltage and eliminating back-gate bias effect

A non-depletion floating layer silicon-on-insulator (NFL SOI) lateral double-diffused metal-oxide-semiconductor (LDMOS) is proposed and the NFL-assisted modulated field (NFLAMF) principle is investigated in this paper. Based on this principle, the floating layer can pin the potential for modulating bulk field. In particular, the accumulated high concentration of holes at the bottom of the NFL can efficiently shield the electric field of the SOI layer and enhance the dielectric field in the buried oxide layer (BOX). At variation of back-gate bias, the shielding charges of NFL can also eliminate back-gate effects. The simulated results indicate that the breakdown voltage (BV) is increased from 315 V to 558 V compared to the conventional reduced surface field (RESURF) SOI (CSOI) LDMOS, yielding a 77% improvement. Furthermore, due to the field shielding effect of the NFL, the device can maintain the same breakdown voltage of 558 V with a thinner BOX to resolve the thermal problem in an SOI device.     

A two-dimensional analytical model for channel potential and threshold voltage of short channel dual material gate lightly doped drain MOSFET

An analytical model for the channel potential and the threshold voltage of the short channel dual-material-gate lightly doped drain （DMG-LDD） metal-oxide-semiconductor field-effect transistor （MOSFET） is presented using the parabolic approximation method. The proposed model takes into account the effects of the LDD region length, the LDD region doping, the lengths of the gate materials and their respective work functions, along with all the major geometrical parameters of the MOSFET. The impact of the LDD region length, the LDD region doping, and the channel length on the channel potential is studied in detail. Furthermore, the threshold voltage of the device is calculated using the minimum middle channel potential, and the result obtained is compared with the DMG MOSFET threshold voltage to show the improvement in the threshold voltage roll-off. It is shown that the DMG-LDD MOSFET structure alleviates the problem of short channel effects （SCEs） and the drain induced barrier lowering （DIBL） more efficiently. The proposed model is verified by comparing the theoretical results with the simulated data obtained by using the commercially available ATLASTM 2D device simulator.     

A new structure and its analytical model for the vertical interface electric field of a partial-SOI high voltage device

A new partial-SOI (PSOI) high voltage device structure called a CI PSOI (charge island PSOI) is proposed for the first time in this paper. The device is characterized by a charge island layer on the interface of the top silicon layer and the dielectric buried layer in which a series of equidistant high concentration n⁺-regions is inserted. Inversion holes resulting from the vertical electric field are located in the spacing between two neighbouring n⁺-regions on the interface by the force with ionized donors in the undepleted n⁺-regions, and therefore effectively enhance the electric field of the dielectric buried layer (E_I) and increase the breakdown voltage (BV), thereby alleviating the self-heating effect (SHE) by the silicon window under the source. An analytical model of the vertical interface electric field for the CI PSOI is presented and the analytical results are in good agreement with the 2D simulation results. The BV and E_I of the CI PSOI LDMOS increase to 631~V and 584~V/μ m from 246~V and 85.8~V/μ m for the conventional PSOI with a lower SHE, respectively. The effects of the structure parameters on the device characteristics are analysed for the proposed device in detail.     

Generalized analytical expressions for the burning velocity in a combustion model with non-constant transport coefficients and several specific heats

We derive new expressions to estimate the burning velocity of a laminar gas flame in a simplified combustion model based on a one-step single reaction with transport coefficients (mass and heat) depending on temperature, and species with different specific heats. These new expressions generalize the bounds and approximations previously derived by Williams, von Karman, Zeldovich and Frank-Kamenetskii, Benguria and Depassier, and the matching asymptotic expansion method in a two zone model. The comparison of the flame speed predicted by these new analytical expressions with that numerically simulated by the full combustion model for a large variety of cases allows us to determine their range of validity. The upper bound based on the Benguria and Depassier method provides very good approximations for the actual propagation speed of combustion flames, being substantially better than the asymptotic method used in the recent papers.