深亚微米金属氧化物场效应晶体管及寄生双极晶体管的总剂量效应研究

为从工艺角度深入研究航空航天用互补金属氧化物半导体(CMOS)工艺混合信号集成电路总剂量辐射损伤机理, 选取国产CMOS 工艺制作的NMOS晶体管及寄生双极晶体管进行了⁶⁰Coγ射线源下的总剂量试验研究. 发现: 1) CMOS工艺中固有的寄生效应导致NMOS晶体管截止区漏电流对总剂量敏感, 随总剂量累积而增 大; 2) 寄生双极晶体管总剂量损伤与常规双极晶体管不同, 表现为对总剂量不敏感, 分析认为两者辐射损伤的差异来源于制作工艺的不同; 3)寄生双极晶体管与NMOS晶体 管的总剂量损伤没有耦合效应; 4)基于上述研究成果, 初步分析CMOS工艺混合信号集成电路中数字模块及模拟模块辐射损伤机制, 认为MOS晶体管截止漏电流增大是导致数字模块功耗增大的主因, 而Bandgap电压基准源模块对总剂量不敏感源于寄生双极晶体管抗总剂量辐射的能力. 关键词： 总剂量效应 N沟道金属氧化物场效应晶体管 寄生双极晶体管 Bandgap基准电压源     

绝缘体上硅金属氧化物半导体场效应晶体管中辐射导致的寄生效应研究

基于⁶⁰Co γ射线源研究了总剂量辐射对绝缘体上硅（silicon on insulator,SOI）金属氧化物半导体场效应晶体管器件的影响.通过对比不同尺寸器件的辐射响应,分析了导致辐照后器件性能退化的不同机制.实验表明：器件的性能退化来源于辐射增强的寄生效应;浅沟槽隔离（shallow trench isolation,STI）寄生晶体管的开启导致了关态漏电流随总剂量呈指数增加,直到达到饱和;STI氧化层的陷阱电荷共享导致了窄沟道器件的阈值电压漂移,而短沟道器件的阈值电压漂移则来自于背栅阈值耦合;在同一工艺下,尺寸较小的器件对总剂量效应更敏感.探讨了背栅和体区加负偏压对总剂量效应的影响,SOI器件背栅或体区的负偏压可以在一定程度上抑制辐射增强的寄生效应,从而改善辐照后器件的电学特性.     

Characteristics of drain-modulated generation current in n-type metal-oxide-semiconductor field-effect transistor

Drain-modulated generation current IDMGinduced by interface traps in an n-type metal-oxide-semiconductor fieldeffect transistor(n MOSFET) is investigated. The formation of IDMGascribes to the change of the Si surface potential φs.This change makes the channel suffer transformation from the inversion state, depletion I state to depletion II state. The simulation result agrees with the experiment in the inversion and depletion I states. In the depletion II state, the theoretical curve goes into saturation, while the experimental curve drops quickly as VDincreases. The reason for this unconformity is that the drain-to-gate voltage VDGlessens φs around the drain corner and controls the falling edge of the IDMG curve.The experiments of gate-modulated generation and recombination currents are also applied to verify the reasonability of the mechanism. Based on this mechanism, a theoretical model of the IDMGfalling edge is set up in which IDMGhas an exponential attenuation relation with VDG. Finally, the critical fitting coefficient t of the experimental curves is extracted. It is found that t = 80 m V = 3k T /q. This result fully shows the accuracy of the above mechanism.     

纳米尺度金属-氧化物半导体场效应晶体管沟道热噪声模型

随着CMOS工艺的发展,热载流子效应对沟道热噪声的影响随着器件尺寸的降低而增大,传统热噪声模型未能准确表征沟道的热噪声.本文通过解能量平衡方程,得到电子温度表达式,并结合沟道漏电流表达式,建立了沟道热噪声模型.利用建立的电子温度表达式,该热噪声模型考虑了热载流子效应的影响,并且在计算热噪声的过程中考虑了电子温度对迁移率降低的影响以及温度梯度对热噪声的影响.通过分析与计算,结果显示,随着器件尺寸的减小,温度梯度对电子温度产生显著影响,使得热载流子效应的影响增大,热载流子效应对热噪声的增长作用超过了迁移率降低对热噪声的减小作用,最终导致热噪声增大.本文建立的沟道热噪声模型可应用于纳米尺寸金属-氧化物半导体场效应晶体管器件的噪声性能分析及建模.     

GaSb p-channel metal-oxide-semiconductor field-effect transistor and its temperature dependent characteristics

GaSb p-channel metal-oxide-semiconductor field-effect transistors(MOSFETs)with an atomic layer deposited Al2O3gate dielectric and a self-aligned Si-implanted source/drain are experimentally demonstrated.Temperature dependent electrical characteristics are investigated.Different electrical behaviors are observed in two temperature regions,and the underlying mechanisms are discussed.It is found that the reverse-bias pn junction leakage of the drain/substrate is the main component of the off-state drain leakage current,which is generation-current dominated in the low temperature regions and is diffusion-current dominated in the high temperature regions.Methods to further reduce the off-state drain leakage current are given.     

SOI metal-oxide-semiconductor field-effect transistor photon detector based on single-hole counting

In this Letter, a scaled-down silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect transistor (MOSFET) is characterized as a photon detector, where photogenerated individual holes are trapped below the negatively biased gate and modulate stepwise the electron current flowing in the bottom channel induced by the positive substrate bias. The output waveforms exhibit clear separation of current levels corresponding to different numbers of trapped holes. Considering this capability of single-hole counting, a small dark count of less than 0.02 s(-1) at room temperature, and low operation voltage of 1 V, SOI MOSFET could be a unique photon-number-resolving detector if the small quantum efficiency were improved.     

The plateau widths of the quantized Hall conductance

A possible mechanism for the normal quantized Hall conductance is suggested from a viewpoint different from Laughlin's theory, and a formula for the widths of the Hall conductance plateaus is presented, which shows good agreement with the recent experimental data by Störmer et al.     

p型金属氧化物半导体场效应晶体管低剂量率辐射损伤增强效应模型研究

对一种非加固4007电路中p型金属氧化物半导体场效应晶体管(PMOSFET)在不同剂量率条件下的电离辐射损伤效应及高剂量率辐照后的退火效应进行了研究. 通过测量不同剂量率条件下PMOSFET的亚阈I-V特性曲线,得到阈值电压漂移量随累积剂量、退火时间的变化关系. 实验发现,此种型号的PMOSFET具有低剂量率辐射损伤增强效应. 通过描述H⁺在氧化层中的输运过程,解释了界面态的形成原因,初步探讨了非加固4007电路中PMOSFET低剂量率辐射损伤增强效应模型. 关键词： p型金属氧化物半导体场效应晶体管 60Co γ射线')" href="#">⁶⁰Co γ射线 电离辐射损伤 低剂量率辐射损伤增强效应     

电离辐射环境下的部分耗尽绝缘体上硅n型金属氧化物半导体场效应晶体管可靠性研究

随着半导体技术的进步, 集成小尺寸绝缘体上硅器件的芯片开始应用到航空航天领域, 使得器件在使用中面临了深空辐射环境与自身常规可靠性的双重挑战. 进行小尺寸器件电离辐射环境下的可靠性试验有助于对器件综合可靠性进行评估. 参照国标GB2689.1-81恒定应力寿命试验与加速寿命试验方法总则进行电应力选取, 对部分耗尽绝缘体上硅n型金属氧化物半导体场效应晶体管进行了电离辐射环境下的常规可靠性研究. 通过试验对比, 定性地分析了氧化物陷阱电荷和界面态对器件敏感参数的影响, 得出了氧化物陷阱电荷和界面态随着时间参数的变化, 在不同阶段对器件参数的影响. 结果表明, 总剂量效应与电应力的共同作用将加剧器件敏感参数的退化, 二者的共同作用远大于单一影响因子.     

Influences of fringing capacitance on threshold voltage and subthreshold swing of a GeOI metal-oxide-semiconductor field-effect transistor

Models of threshold voltage and subthreshold swing, including the fringing-capacitance effects between the gate electrode and the surface of the source/drain region, are proposed. The validity of the proposed models is confirmed by the good agreement between the simulated results and the experimental data. Based on the models, some factors impacting the threshold voltage and subthreshold swing of a GeOI metal-oxide-semiconductor field-effect transistor(MOSFET) are discussed in detail and it is found that there is an optimum thickness of gate oxide for definite dielectric constant of gate oxide to obtain the minimum subthreshold swing. As a result, it is shown that the fringing-capacitance effect of a shortchannel GeOI MOSFET cannot be ignored in calculating the threshold voltage and subthreshold swing.     

具有P型覆盖层新型超级结横向双扩散功率器件

为了设计功率集成电路所需要的低功耗横向双扩散金属氧化物半导体器件(lateral double-diffused MOSFET), 在已有的N型缓冲层超级结LDMOS(N-buffered-SJ-LDMOS)结构基础上, 提出了一种具有P型覆盖层新型超级结LDMOS结构(P-covered-SJ-LDMOS). 这种结构不但能够消除传统的N沟道SJ-LDMOS由于P型衬底产生的衬底辅助耗尽问题, 使得超级结层的N区和P区的电荷完全补偿, 而且还能利用覆盖层的电荷补偿作用, 提高N型缓冲层浓度, 从而降低了器件的比导通电阻. 利用三维仿真软件ISE分析表明, 在漂移区长度均为10 μm的情况下, P-covered-SJ-LDMOS的比导通电阻较一般SJ-LDMOS结构降低了59%左右, 较文献提出的N型缓冲层 SJ-LDMOS(N-buffered-SJ-LDMOS)结构降低了43%左右.     

Three-dimensional electronic structures in the Si inversion layer of nanoscale metal-oxide-semiconductor field-effect transistors

The three-dimensional electronic structure in the Si inversion layer of nanoscale metal-oxide-semiconductor field-effect transistors (MOSFETs) were calculated by using a self-consistent method. The electronic energy states and the probability density functions in a three-dimensionally confined quantum structure were determined. The energy states strongly depended on the thickness of the thin oxide layer and the applied gate voltage. The few electrons occupying the Si inversion layer significantly affected the electric potential profile of the inversion layer, and a small variation in the oxide thickness dramatically changed the electronic properties in the Si inversion layer. These results can help in understanding the electronic structures in Si inversion layers of nanoscale MOSFETs.     

Modeling of a triple reduced surface field silicon-on-insulator lateral double-diffused metal–oxide–semiconductor field-effect transistor with low on-state resistance

An analytical model for a novel triple reduced surface field(RESURF) silicon-on-insulator(SOI) lateral doublediffused metal–oxide–semiconductor(LDMOS) field effect transistor with n-type top(N-top) layer, which can obtain a low on-state resistance, is proposed in this paper. The analytical model for surface potential and electric field distributions of the novel triple RESURF SOI LDMOS is presented by solving the two-dimensional(2D) Poisson's equation, which can also be applied to single, double and conventional triple RESURF SOI structures. The breakdown voltage(BV) is formulized to quantify the breakdown characteristic. Besides, the optimal integrated charge of N-top layer(Q_(ntop)) is derived, which can give guidance for doping the N-top layer. All the analytical results are well verified by numerical simulation results,showing the validity of the presented model. Hence, the proposed model can be a good tool for the device designers to provide accurate first-order design schemes and physical insights into the high voltage triple RESURF SOI device with N-top layer.     

The effect of body bias of the metal-oxide-semiconductor field-effect transistor in the resistive network on spatial current distribution in a bio-inspired complementary metal-oxide-semiconductor vision chip

Complementary metal-oxide-semiconductor (CMOS) vision chips for edge detection based on a resistive circuit have recently been developed. These chips help in the creation of neuromorphic systems of a compact size, high speed of operation, and low power dissipation. The output of the vision chip depends predominantly upon the electrical characteristics of the resistive network which consists of a resistive circuit. In this paper, the body effect of the metal-oxide-semiconductor field-effect transistor for current distribution in a resistive circuit is discussed with a simple model. In order to evaluate the model, two 160 × 120 CMOS vision chips have been fabricated using a standard CMOS technology. The experimental results nicely match our prediction.     

Ultra-low specific on-resistance high-voltage vertical double diffusion metal–oxide–semiconductor field-effect transistor with continuous electron accumulation layer

A new ultra-low specific on-resistance(Ron,sp) vertical double diffusion metal–oxide–semiconductor field-effect transistor(VDMOS) with continuous electron accumulation(CEA) layer, denoted as CEA-VDMOS, is proposed and its new current transport mechanism is investigated. It features a trench gate directly extended to the drain, which includes two PN junctions. In on-state, the electron accumulation layers are formed along the sides of the extended gate and introduce two continuous low-resistance current paths from the source to the drain in a cell pitch. This mechanism not only dramatically reduces the Ron,sp but also makes the Ron,sp almost independent of the n-pillar doping concentration(Nn). In off-state, the depletion between the n-pillar and p-pillar within the extended trench gate increases the Nn, and further reduces the Ron,sp.Especially, the two PN junctions within the trench gate support a high gate–drain voltage in the off-state and on-state, respectively. However, the extended gate increases the gate capacitance and thus weakens the dynamic performance to some extent. Therefore, the CEA-VDMOS is more suitable for low and medium frequencies application. Simulation indicates that the CEA-VDMOS reduces the Ron,sp by 80% compared with the conventional super-junction VDMOS(CSJ-VDMOS)at the same high breakdown voltage(BV).     

Temperature dependent conductive behavior of pentacene in organic field-effect transistor

Impedance characterization at different temperature has been used to investigate the conductive behavior of pentacene as the semiconductor layer in organic field-effect transistor. It has been found that the pentacene exhibits an enhancement in conductivity by heating following an Arrhenius law with an activation energy transition from 0.004 to 0.018 eV at 323 K, which originates from band tail hopping that occurs around the Fermi edge.     

Quasi-two-dimensional threshold voltage model for junctionless cylindrical surrounding gate metal-oxide-semiconductor field-effect transistor with dual-material gate

Based on the quasi-two-dimensional(2D) solution of Poisson’s equation in two continuous channel regions, an analytical threshold voltage model for short-channel junctionless dual-material cylindrical surrounding-gate(JLDMCSG) metal-oxide-semiconductor field-effect transistor(MOSFET) is developed. Using the derived model, channel potential distribution, horizontal electrical field distribution, and threshold voltage roll-off of JLDMCSG MOSFET are investigated. Compared with junctionless single-material CSG(JLSGCSG) MOSFET, JLDMCSG MOSFET can effectively suppress short-channel effects and simultaneously improve carrier transport efficiency. It is also revealed that threshold voltage rolloff of JLDMCSG can be significantly reduced by adopting both a small oxide thickness and a small silicon channel radius. The model is verified by comparing its calculated results with that obtained from three-dimensional(3D) numerical device simulator ISE.     

具有半绝缘多晶硅完全三维超结横向功率器件

为了突破传统LDMOS (lateral double-diffused MOSFET)器件击穿电压与比导通电阻的硅极限的2.5 次方关系, 降低LDMOS器件的功率损耗, 提高功率集成电路的功率驱动能力, 提出了一种具有半绝缘多晶硅SIPOS (semi-insulating poly silicon)覆盖的完全3 D-RESURF (three-dimensional reduced surface field)新型Super Junction-LDMOS结构(SIPOS SJ-LDMOS). 这种结构利用SIPOS的电场调制作用使SJ-LDMOS的表面电场分布均匀, 将器件单位长度的耐压量提高到19.4 V/μupm; 覆盖于漂移区表面的SIPOS使SJ-LDMOS沿三维方向均受到电场调制, 实现了LDMOS的完全3 D-RESURF效应, 使更高浓度的漂移区完全耗尽而达到高的击穿电压; 当器件开态工作时, 覆盖于薄场氧化层表面的SIPOS的电场作用使SJ-LDMOS的漂移区表面形成多数载流子积累, 器件比导通电阻降低. 利用器件仿真软件ISE分析获得, 当SIPOS SJ-LDMOS的击穿电压为388 V时, 比导通电阻为20.87 mΩ·cm², 相同结构参数条件下, N-buffer SJ-LDMOS的击穿电压为287 V, 比导通电阻为31.14 mΩ·cm²; 一般SJ-LDMOS 的击穿电压仅为180 V, 比导通电阻为71.82 mΩ·cm².     

具有poly-Si$lt;sub$gt;1-$lt;i$gt;x$lt;/i$gt;$lt;/sub$gt;Ge$lt;sub$gt;$lt;i$gt;x$lt;/i$gt;$lt;/sub$gt;栅的应变SiGep型金属氧化物半导体场效应晶体管阈值电压漂移模型研究

针对具有poly-Si_1-xGe_x栅的应变SiGe p型金属氧化物半导体场效应晶体管(PMOSFET), 研究了其垂直电势与电场分布, 建立了考虑栅耗尽的poly-Si_1-xGe_x栅情况下该器件的等效栅氧化层厚度模型, 并利用该模型分析了poly-Si_1-xGe_x栅及应变SiGe层中Ge组分对等效氧化层厚度的影响. 研究了应变SiGe PMOSFET热载流子产生的机理及其对器件性能的影响, 以及引起应变SiGe PMOSFET阈值电压漂移的机理, 并建立了该器件阈值电压漂移模型, 揭示了器件阈值电压漂移随电应力施加时间、栅极电压、poly-Si_1-xGe_x栅及应变SiGe层中Ge组分的变化关系. 并在此基础上进行了实验验证, 在电应力施加10000 s时, 阈值电压漂移0.032 V, 与模拟结果基本一致, 为应变SiGe PMOSFET及相关电路的设计与制造提供了重要的理论与实践基础. 关键词： 应变SiGep型金属氧化物半导体场效应晶体管 1-xGe_x栅')" href="#">poly-Si_1-xGe_x栅 热载流子 阈值电压     

γ射线总剂量辐照对单轴应变Si纳米n型金属氧化物半导体场效应晶体管栅隧穿电流的影响

基于γ射线辐照条件下单轴应变Si纳米n型金属氧化物半导体场效应晶体管(NMOSFET)载流子的微观输运机制,揭示了单轴应变Si纳米NMOSFET器件电学特性随总剂量辐照的变化规律,同时基于量子机制建立了小尺寸单轴应变Si NMOSFET在γ射线辐照条件下的栅隧穿电流模型,应用Matlab对该模型进行了数值模拟仿真,探究了总剂量、器件几何结构参数、材料物理参数等对栅隧穿电流的影响.此外,通过实验进行对比,该模型仿真结果和总剂量辐照实验测试结果基本符合,从而验证了模型的可行性.本文所建模型为研究纳米级单轴应变Si NMOSFET应变集成器件可靠性及电路的应用提供了有价值的理论指导与实践基础.