Two-dimensional threshold voltage model of nanoscale silicon-on-insulator tunneling field-effect transistor

The tunneling field-effect transistor (TFET) is a potential candidate for the post-CMOS era. In this paper, a threshold voltage model is developed for this new kind of device. First, two-dimensional (2D) models are used to describe the distributions of potential and electric field in the channel and two depletion regions. Then based on the physical definition of threshold voltage for the nanoscale TFET, the threshold voltage model is developed. The accuracy of the proposed model is verified by comparing the calculated results with the 2D device simulation data. It has been demonstrated that the effects of varying the device parameters can easily be investigated using the model presented in this paper. This threshold voltage model provides a valuable reference to the TFET device design, simulation, and fabrication.     

Characteristics of cylindrical surrounding-gate GaAs_xSb_(1-x)/In_yGa_(1-y)As heterojunction tunneling field-effect transistors

A Ⅲ-Ⅴ heterojunction tunneling field-effect transistor(TFET) can enhance the on-state current effectively,and GaAs_xSb_1_x/In_yGa_1_yAs heterojunction exhibits better performance with the adjustable band alignment by modulating the alloy composition.In this paper,the performance of the cylindrical surrounding-gate GaAs_xSb_1_x/In_yGa_1_yAs heterojunction TFET with gate-drain underlap is investigated by numerical simulation.We validate that reducing drain doping concentration and increasing gate-drain underlap could be effective ways to reduce the off-state current and subthreshold swing(SS),while increasing source doping concentration and adjusting the composition of GaAs_xSb_1_xIn_yGa_1_yAs can improve the on-state current.In addition,the resonant TFET based on GaAs_xSb_1_x/In_yGa_1_yAs is also studied,and the result shows that the minimum and average of SS reach 11 mV/decade and 20 mV/decade for five decades of drain current,respectively,and is much superior to the conventional TFET.     

InGaAs/InP heterojunction-channel tunneling field-effect transistor for ultra-low operating and standby power application below supply voltage of 0.5 V

An In_0.53Ga_0.47As/InP heterojunction-channel tunneling field-effect transistor (TFET) with enhanced subthreshold swing (S) and on/off current ratio (I_on/I_off) is studied. The proposed TFET achieves remarkable characteristics including S of 16.5 mV/dec, on-state current (I_on) of 421 μA/μm, I_on/I_off of 1.2 × 10¹² by design optimization in doping type of In_0.53Ga_0.47As channel at low gate (V_GS) and drain voltages (V_DS) of 0.5 V. Comparable performances are maintained at V_DS below 0.5 V. Moreover, an extremely fast switching below 100 fs is accomplished by the device. It is confirmed that the proposed TFET has strong potentials for the ultra-low operating power and high-speed electron device.     

Influence of trap-assisted tunneling on trap-assisted tunneling current in double gate tunnel field-effect transistor

Trap-assisted tunneling(TAT) has attracted more and more attention, because it seriously affects the sub-threshold characteristic of tunnel field-effect transistor(TFET). In this paper, we assess subthreshold performance of double gate TFET(DG-TFET) through a band-to-band tunneling(BTBT) model, including phonon-assisted scattering and acoustic surface phonons scattering. Interface state density profile(D_(it)) and the trap level are included in the simulation to analyze their effects on TAT current and the mechanism of gate leakage current.     

电离辐射环境下的部分耗尽绝缘体上硅n型金属氧化物半导体场效应晶体管可靠性研究

随着半导体技术的进步, 集成小尺寸绝缘体上硅器件的芯片开始应用到航空航天领域, 使得器件在使用中面临了深空辐射环境与自身常规可靠性的双重挑战. 进行小尺寸器件电离辐射环境下的可靠性试验有助于对器件综合可靠性进行评估. 参照国标GB2689.1-81恒定应力寿命试验与加速寿命试验方法总则进行电应力选取, 对部分耗尽绝缘体上硅n型金属氧化物半导体场效应晶体管进行了电离辐射环境下的常规可靠性研究. 通过试验对比, 定性地分析了氧化物陷阱电荷和界面态对器件敏感参数的影响, 得出了氧化物陷阱电荷和界面态随着时间参数的变化, 在不同阶段对器件参数的影响. 结果表明, 总剂量效应与电应力的共同作用将加剧器件敏感参数的退化, 二者的共同作用远大于单一影响因子.     

具有poly-Si$lt;sub$gt;1-$lt;i$gt;x$lt;/i$gt;$lt;/sub$gt;Ge$lt;sub$gt;$lt;i$gt;x$lt;/i$gt;$lt;/sub$gt;栅的应变SiGep型金属氧化物半导体场效应晶体管阈值电压漂移模型研究

针对具有poly-Si_1-xGe_x栅的应变SiGe p型金属氧化物半导体场效应晶体管(PMOSFET), 研究了其垂直电势与电场分布, 建立了考虑栅耗尽的poly-Si_1-xGe_x栅情况下该器件的等效栅氧化层厚度模型, 并利用该模型分析了poly-Si_1-xGe_x栅及应变SiGe层中Ge组分对等效氧化层厚度的影响. 研究了应变SiGe PMOSFET热载流子产生的机理及其对器件性能的影响, 以及引起应变SiGe PMOSFET阈值电压漂移的机理, 并建立了该器件阈值电压漂移模型, 揭示了器件阈值电压漂移随电应力施加时间、栅极电压、poly-Si_1-xGe_x栅及应变SiGe层中Ge组分的变化关系. 并在此基础上进行了实验验证, 在电应力施加10000 s时, 阈值电压漂移0.032 V, 与模拟结果基本一致, 为应变SiGe PMOSFET及相关电路的设计与制造提供了重要的理论与实践基础. 关键词： 应变SiGep型金属氧化物半导体场效应晶体管 1-xGe_x栅')" href="#">poly-Si_1-xGe_x栅 热载流子 阈值电压     

Heteromaterial-gate line tunnel field-effect transistor based on Si/Ge heterojunction

A Si/Ge heterojunction line tunnel field-effect transistor(LTFET) with a symmetric heteromaterial gate is proposed.Compared to single-material-gate LTFETs, the heteromaterial gate LTFET shows an off-state leakage current that is three orders of magnitude lower, and steeper subthreshold characteristics, without degradation in the on-state current. We reveal that these improvements are due to the induced local potential barrier, which arises from the energy-band profile modulation effect. Based on this novel structure, the impacts of the physical parameters of the gap region between the pocket and the drain, including the work-function mismatch between the pocket gate and the gap gate, the type of dopant, and the doping concentration, on the device performance are investigated. Simulation and theoretical calculation results indicate that the gap gate material and n-type doping level in the gap region should be optimized simultaneously to make this region fully depleted for further suppression of the off-state leakage current.     

A model for the electrical characteristics of metal-ferroelectric-insulator-semiconductor field-effect transistor

An improved theoretical model on the electrical characteristics of metal-ferroelectric-insulator-semiconductor field-effect transistor (MFIS-FET) has been proposed by considering the history-dependent electric field effect and the mobility model. The capacitance-voltage (C-V) characteristics of MFIS structure is evaluated by combining the switching physics of ferroelectric with the silicon physics, and the drain current-gate voltage (I_D-V_GS) and drain current-drain voltage (I_D-V_DS) characteristics of MFIS-FET are modeled by combining the switching physics of ferroelectric with Pao and Sah’s double integral. For two MFIS-FETs with SrBi₂Ta₂O₉ and (Bi,La)₄Ti₃O₁₂ ferroelectric layers, the C-V, I_D-V_GS and I_D-V_DS characteristics are simulated by using the improved model, and the results are more consistent with the previous experiment than those based on Lue model, indicating that the improved model is suitable for simulating the electrical characteristics of MFIS-FET. This work is expected to provide some guidance to the design and performance improvement of MFIS structure devices.     

Temperature dependent conductive behavior of pentacene in organic field-effect transistor

Impedance characterization at different temperature has been used to investigate the conductive behavior of pentacene as the semiconductor layer in organic field-effect transistor. It has been found that the pentacene exhibits an enhancement in conductivity by heating following an Arrhenius law with an activation energy transition from 0.004 to 0.018 eV at 323 K, which originates from band tail hopping that occurs around the Fermi edge.     

Resonant cavity-enhanced quantum dot field-effect transistor as a single-photon detector

A resonant cavity-enhanced （RCE） quantum dot （QD） field-effect transistor （RCEQDFET） is designed for single- photon detection in this paper. Adding distributed Bragg reflection （DBR） mirrors to the single-photon detector （SPD）, we improve the light absorption efficiency of the SPD. The effects of the reflectivity of the mirrors, the thickness and light absorption coefficient of the absorbing layer on the detector＇s light absorption efficiency are investigated, and the resonant cavity is determined by using the air/semiconductor interface as the mirror on the top. Through analyzing the relationship between the refractive index of AlxGal_xAs and A1 component, we choose A1As/Alo.15Gao.85As as the material of the mirror on the bottom. The pairs of A1As/Alo.15Gao.85As film are further determined to be 21 by calculating the reflectivity of the mirror. The detector is fabricated from semiconductor heterostructures grown by molecular beam epitaxy. The reflection spectrum, photoluminescence （PL） spectrum, photocurrent response, and channel current of the detector are tested and the results show that the RCEQDFET-SPD designed in this paper has better performances in photonic response and wavelength selection.     

高$lt;i$gt;k$lt;/i$gt;栅介质小尺寸全耗尽绝缘体上锗p型金属氧化物半导体场效应晶体管漏源电流模型

通过求解沟道的二维泊松方程得到沟道表面势和沟道反型层电荷, 建立了高k栅介质小尺寸绝缘体上锗(GeOI) p型金属氧化物半导体场效应晶体管(PMOSFET)的漏源电流解析模型. 模型包括了速度饱和效应、迁移率调制效应和沟长调制效应, 同时考虑了栅氧化层和埋氧层与沟道界面处的界面陷阱电荷、氧化层固定电荷对漏源电流的影响. 在饱和区和非饱和区, 漏源电流模拟结果与实验数据符合得较好, 证实了模型的正确性和实用性. 利用建立的漏源电流模型模拟分析了器件主要结构和物理参数对跨导、漏导、截止频率和电压增益的影响, 对GeOI PMOSFET的设计具有一定的指导作用. 关键词： 绝缘体上锗p型金属氧化物半导体场效应晶体管 漏源电流模型 跨导 截止频率     

Monolithic integration of an AlGaN/GaN metalinsulator field-effect transistor with an ultra-low voltage-drop diode for self-protection

In this paper,we present a monolithic integration of a self-protected AlGaN/GaN metal-insulator field-effect transistor(MISFET).An integrated field-controlled diode on the drain side of the AlGaN/GaN MISFET features a selfprotected function for a reverse bias.This diode takes advantage of the recessed-barrier enhancement-mode technique to realize an ultra-low voltage drop and a low turn-ON voltage.In the smart monolithic integration,this integrated diode can block a reverse bias(> 70 V/μm) and suppress the leakage current(< 5 × 10-11 A/mm).Compared with conventional monolithic integration,the numerical results show that the MISFET integrated with a field-controlled diode leads to a good performance for smart power integration.And the power loss is lower than 50% in conduction without forward current degeneration.     

Monolithic integration of AlGaN/GaN metal—insulator field-effect transistor with ultra-low voltage-drop diode for self-protection

In this paper, we present a monolithic integration of self-protected AlGaN/GaN metal-insulator field-effect transistor (MISFET). An integrated field-controlled diode on the drain side of the AlGaN/GaN MISFET features self-protected function at reverse bias. This diode takes advantage of the recessed-barrier enhancement-mode technique to realize an ultra-low voltage drop and a low turn-ON voltage. In the smart monolithic integration, this integrated diode can block reverse bias (>70 V/μm) and suppress the leakage current (<5×10^-11 A/mm). Compared with conventional monolithic integration, the numerical results show that the MISFET integrated with a field-controlled diode leads to a good performance for smart power integration. And the power loss is lower than 50% in conduction without forward current degeneration.     

Design and analysis of Si-based arch-shaped gate-all-around (GAA) tunneling field-effect transistor (TFET)

In this work, a Si-based arch-shaped gate-all-around (GAA) tunneling field-effect transistor (TFET) has been designed and analyzed. Various studies on III–V compound semiconductor materials for applications in TFET devices have been made and we adopt one of them to perform a physical design for boosting the tunneling probability. The GAA structure has a partially open region for extending the tunneling area and the channel is under the GAA region, which makes it an arch-shaped GAA structure. We have performed the design optimization with variables of epitaxy channel thickness (t_epi) and height of source region (H_source) in the Si-based TFET. The designed arch-shaped GAA TFET based on Si platform demonstrates excellent performances for low-power (LP) applications including on-state current (I_on) of 694 μA/μm, subthreshold swing (S) of 7.8 mV/dec, threshold voltage (V_t) of 0.1 V, current gain cut-off frequency (f_T) of 12 GHz, and maximum oscillation frequency (f_max) of 283 GHz.     

An analytical threshold voltage model for dual-strained channel PMOSFET

Based on the analysis of vertical electric potential distribution across the dual-channel strained p-type Si/strained Si 1-x Ge x /relaxd Si 1-y Ge y (s-Si/s-SiGe/Si 1-y Ge y) metal-oxide-semiconductor field-effect transistor (PMOSFET),an-alytical expressions of the threshold voltages for buried channel and surface channel are presented.And the maximum allowed thickness of s-Si is given,which can ensure that the strong inversion appears earlier in the buried channel (compressive strained SiGe) than in the surface channel (tensile strained Si),because the hole mobility in the buried channel is higher than that in the surface channel.Thus they offer a good accuracy as compared with the results of device simulator ISE.With this model,the variations of threshold voltage and maximum allowed thickness of s-Si with design parameters can be predicted,such as Ge fraction,layer thickness,and doping concentration.This model can serve as a useful tool for p-channel s-Si/s-SiGe/Si 1-y Ge y metal-oxide-semiconductor field-effect transistor (MOSFET) designs.     

Design optimization of tunneling field-effect transistor based on silicon nanowire PNPN structure and its radio frequency characteristics

Recently, a number of semiconductor devices have been widely researched in order to make breakthroughs from the short-channel effects (SCEs) and high standby power dissipation of the conventional metal-oxide-semiconductor field-effect transistors (MOSFETs). In this paper, a design optimization for the silicon nanowire tunneling field-effect transistor (SNW TFET) based on PNPN multi-junction structure and its radio frequency (RF) performances are presented by using technology computer-aided design (TCAD) simulations. The design optimization was carried out in terms of primary direct-current (DC) parameters such as on-current (I_on), off-current (I_off), current ratio (I_on/I_off), and subthreshold swing (SS). Based on the parameters from optimized DC characteristics, basic radio frequency (RF) performances such as cut-off frequency (f_T) and maximum oscillation frequency (f_max) were analyzed. The simulated device had a channel length of 60 nm and a SNW radius of 10 nm. The design variable was width of the n-doped layer. For an optimally designed PNPN SNW TFET, SS of 34 mV/dec and I_on of 35 μA/μm were obtained. For this device, f_T and f_max were 80 GHz and 800 GHz, respectively.     

改进型异质栅对深亚微米栅长碳化硅MESFET特性影响

基于器件物理分析方法,结合高场迁移率、肖特基栅势垒降低、势垒隧穿等物理模型, 分析了改进型异质栅结构对深亚微米栅长碳化硅肖特基栅场效应晶体管沟道电势、 夹断电压以及栅下电场分布的影响.通过与传统栅结构器件特性的对比表明, 异质栅结构在碳化硅肖特基栅场效应晶体管的沟道电势中引入了多阶梯分布,加强了近源端电场; 另一方面,相比于双栅器件,改进型异质栅器件沟道最大电势的位置远离源端, 因此载流子在沟道中加速更快,在一定程度上屏蔽了漏压引起的电势变化,更好抑制了短沟道效应. 此外,研究了不同结构参数的异质栅对短沟道器件特性的影响,获得了优化的设计方案, 减小了器件的亚阈值倾斜因子.为发挥碳化硅器件在大功率应用中的优势,设计了非对称异质栅结构, 改善了栅电极边缘的电场分布,提高了小栅长器件的耐压.     

Analytical threshold voltage model for strained silicon GAA-TFET

Tunnel field effect transistors(TFETs) are promising devices for low power applications.An analytical threshold voltage model,based on the channel surface potential and electric field obtained by solving the 2D Poisson's equation,for strained silicon gate all around TFETs is proposed.The variation of the threshold voltage with device parameters,such as the strain(Ge mole fraction x),gate oxide thickness,gate oxide permittivity,and channel length has also been investigated.The threshold voltage model is extracted using the peak transconductance method and is verified by good agreement with the results obtained from the TCAD simulation.     

A high voltage silicon-on-insulator lateral insulated gate bipolar transistor with a reduced cell-pitch

A high voltage( 600 V) integrable silicon-on-insulator(SOI) trench-type lateral insulated gate bipolar transistor(LIGBT) with a reduced cell-pitch is proposed.The LIGBT features multiple trenches(MTs):two oxide trenches in the drift region and a trench gate extended to the buried oxide(BOX).Firstly,the oxide trenches enhance electric field strength because of the lower permittivity of oxide than that of Si.Secondly,oxide trenches bring in multi-directional depletion,leading to a reshaped electric field distribution and an enhanced reduced-surface electric-field(RESURF) effect.Both increase the breakdown voltage(BV).Thirdly,oxide trenches fold the drift region around the oxide trenches,leading to a reduced cell-pitch.Finally,the oxide trenches enhance the conductivity modulation,resulting in a high electron/hole concentration in the drift region as well as a low forward voltage drop(Von).The oxide trenches cause a low anode-cathode capacitance,which increases the switching speed and reduces the turn-off energy loss(Eoff).The MT SOI LIGBT exhibits a BV of 603 V at a small cell-pitch of 24 μm,a Von of 1.03 V at 100 A/cm-2,a turn-off time of 250 ns and Eoff of 4.1×10?3 mJ.The trench gate extended to BOX synchronously acts as dielectric isolation between high voltage LIGBT and low voltage circuits,simplifying the fabrication processes.     

Study of top and bottom contact resistance in one organic field-effect transistor

This paper reports that the organic field-effect transistors with hybrid contact geometry were fabricated, in which the top electrodes and the bottom electrodes were combined in parallel resistances within one transistor. With the facility of the novel structure, the difference of contact resistance between the top contact geometry and the bottom contact geometry was studied. The hybrid contact devices showed similar characteristics with the top contact configuration devices, which provide helpful evidence on the lower contact resistance of the top contact configuration device. The origin of the different contact resistance between the top contact device and the bottom contact device was discussed.