背栅效应对SOI横向高压器件击穿特性的影响

提出一种SOI基背栅体内场降低BG REBULF(back-gate reduced BULk field)耐压技术. 其机理是背栅电压诱生界面电荷，调制有源区电场分布，降低体内漏端电场，提高体内源端电场，从而突破习用结构的纵向耐压限制，提高器件的击穿电压. 借助二维数值仿真，分析背栅效应对厚膜高压SOI LDMOS (>600V) 击穿特性的影响，在背栅电压为330V时，实现器件击穿电压1020V，较习用结构提高47.83%. 该技术的提出，为600V以上级SOI基高压功率器件和高压集成电路的实现提供了一种新的设计思路. 关键词： SOI 背栅 体内场降低 LDMOS     

Analysis of the breakdown mechanism for an ultra high voltage high-side thin layer silicon-on-insulator p-channel low-density metal-oxide semiconductor

This paper discusses the breakdown mechanism and proposes a new simulation and test method of breakdown voltage(BV) for an ultra-high-voltage(UHV) high-side thin layer silicon-on-insulator(SOI) p-channel lateral double-diffused metal-oxide semiconductor(LDMOS).Compared with the conventional simulation method,the new one is more accordant with the actual conditions of a device that can be used in the high voltage circuit.The BV of the SOI p-channel LDMOS can be properly represented and the effect of reduced bulk field can be revealed by employing the new simulation method.Simulation results show that the off-state(on-state) BV of the SOI p-channel LDMOS can reach 741(620) V in the 3-μm-thick buried oxide layer,50-μm-length drift region,and at 400 V back-gate voltage,enabling the device to be used in a 400 V UHV integrated circuit.     

New SOI power device with multi-region high-concentration fixed interface charge and the model of breakdown voltage

A new SOI power device with multi-region high-concentration fixed charge(MHFC) is reported. The MHFC is formed through implanting Cs or I ion into the buried oxide layer(BOX), by which the high-concentration dynamic electrons and holes are induced at the top and bottom interfaces of BOX. The inversion holes can enhance the vertical electric field and raise the breakdown voltage since the drain bias is mainly generated from the BOX. A model of breakdown voltage is developed, from which the optimal spacing has also been obtained. The numerical results indicate that the breakdown voltage of device proposed is increased by 287% in comparison to that of conventional LDMOS.     

A novel P-channel SOI LDMOS structure with non-depletion potential-clamped layer

A novel structure is proposed for doubling the vertical breakdown voltage of silicon-on-insulator(SOI) devices. In this new structure, the conventional buried oxide(BOX) in an SOI device is split into two sections: the source-section BOX and the drain-section BOX. A highly-doped Si layer, referred to as a non-depletion potential-clamped layer(NPCL), is positioned under and close to the two BOX sections. In the split BOXes and the Si region above the BOXes, the blocking voltage(BV) is divided into two parts by the NPCL. The voltage in the NPCL is clamped to be nearly half of the drain voltage. When the drain voltage approaches a breakdown value, the voltage sustained by the source-section BOX and the Si region under the source are nearly the same as the voltage sustained by the drain-section BOX and the Si region under the drain. The vertical BV is therefore almost doubled. The effectiveness of this new structure was verified for a P-channel SOI lateral double-diffused metal-oxide semiconductor(LDMOS) and can be applied to other high-voltage SOI devices. The simulation results show that the BV in an NPCL P-channel SOI LDMOS is improved by 55% and the specific on-resistance(Ron,sp) is reduced by 69% in comparison to the conventional structure.     

Partial-SOI high voltage P-channel LDMOS with interface accumulation holes

A new partial SOI (silion-on-insulator) (PSOI) high voltage P-channel LDMOS (lateral double-diffused metal-oxide semiconductor) with an interface hole islands (HI) layer is proposed and its breakdown characteristics are investigated theoretically. A high concentration of charges accumulate on the interface, whose density changes with the negative drain voltage, which increase the electric field (E_I) in the dielectric buried oxide layer (BOX) and modulate the electric field in drift region . This results in the enhancement of the breakdown voltage (BV). The values of E_I and BV of an HI PSOI with a 2-μm thick SOI layer over a 1-μm thick buried layer are 580V/μm and -582 V, respectively, compared with 81.5 V/μm and -123 V of a conventional PSOI. Furthermore, the Si window also alleviates the self-heating effect (SHE). Moreover, in comparison with the conventional device, the proposed device exhibits low on-resistance.     

Compound buried layer SOI high voltage device with a step buried oxide

A silicon-on-insulator (SOI) high performance lateral double-diffusion metal oxide semiconductor (LDMOS) on a compound buried layer (CBL) with a step buried oxide (SBO CBL SOI) is proposed.The step buried oxide locates holes in the top interface of the upper buried oxide (UBO) layer.Furthermore,holes with high density are collected in the interface between the polysilicon layer and the lower buried oxide (LBO) layer.Consequently,the electric fields in both the thin LBO and the thick UBO are enhanced by these holes,leading to an improved breakdown voltage.The breakdown voltage of the SBO CBL SOI LDMOS increases to 847 V from the 477 V of a conventional SOI with the same thicknesses of SOI layer and the buried oxide layer.Moreover,SBO CBL SOI can also reduce the self-heating effect.     

Modeling of a triple reduced surface field silicon-on-insulator lateral double-diffused metal–oxide–semiconductor field-effect transistor with low on-state resistance

An analytical model for a novel triple reduced surface field(RESURF) silicon-on-insulator(SOI) lateral doublediffused metal–oxide–semiconductor(LDMOS) field effect transistor with n-type top(N-top) layer, which can obtain a low on-state resistance, is proposed in this paper. The analytical model for surface potential and electric field distributions of the novel triple RESURF SOI LDMOS is presented by solving the two-dimensional(2D) Poisson's equation, which can also be applied to single, double and conventional triple RESURF SOI structures. The breakdown voltage(BV) is formulized to quantify the breakdown characteristic. Besides, the optimal integrated charge of N-top layer(Q_(ntop)) is derived, which can give guidance for doping the N-top layer. All the analytical results are well verified by numerical simulation results,showing the validity of the presented model. Hence, the proposed model can be a good tool for the device designers to provide accurate first-order design schemes and physical insights into the high voltage triple RESURF SOI device with N-top layer.     

Improving breakdown voltage performance of SOI power device with folded drift region

A novel silicon-on-insulator(SOI) high breakdown voltage(BV) power device with interlaced dielectric trenches(IDT) and N/P pillars is proposed. In the studied structure, the drift region is folded by IDT embedded in the active layer,which results in an increase of length of ionization integral remarkably. The crowding phenomenon of electric field in the corner of IDT is relieved by the N/P pillars. Both traits improve two key factors of BV, the ionization integral length and electric field magnitude, and thus BV is significantly enhanced. The electric field in the dielectric layer is enhanced and a major portion of bias is borne by the oxide layer due to the accumulation of inverse charges(holes) at the corner of IDT.The average value of the lateral electric field of the proposed device reaches 60 V/μm with a 10 μm drift length, which increases by 200% in comparison to the conventional SOI LDMOS, resulting in a breakdown voltage of 607 V.     

Ultra-low on-resistance high voltage (>600 V) SOI MOSFET with a reduced cell pitch

A low specific on-resistance (R S,on) silicon-on-insulator (SOI) trench MOSFET (metal-oxide-semiconductor-field-effect-transistor) with a reduced cell pitch is proposed.The lateral MOSFET features multiple trenches:two oxide trenches in the drift region and a trench gate extended to the buried oxide (BOX) (SOI MT MOSFET).Firstly,the oxide trenches increase the average electric field strength along the x direction due to lower permittivity of oxide compared with that of Si;secondly,the oxide trenches cause multiple-directional depletion,which improves the electric field distribution and enhances the reduced surface field (RESURF) effect in the SOI layer.Both of them result in a high breakdown voltage (BV).Thirdly,the oxide trenches cause the drift region to be folded in the vertical direction,leading to a shortened cell pitch and a reduced R S,on.Fourthly,the trench gate extended to the BOX further reduces R S,on,owing to the electron accumulation layer.The BV of the MT MOSFET increases from 309 V for a conventional SOI lateral double diffused metal-oxide semiconductor (LDMOS) to 632 V at the same half cell pitch of 21.5 μm,and R S,on decreases from 419 m · cm 2 to 36.6 m · cm 2.The proposed structure can also help to dramatically reduce the cell pitch at the same breakdown voltage.     

A-188 V 7.2Ω·mm~2,P-channel high voltage device formed on an epitaxy-SIMOX substrate

This paper proposes a new n +-charge island (NCI) P-channel lateral double diffused metal-oxide semiconductor (LDMOS) based on silicon epitaxial separation by implantation oxygen (E-SIMOX) substrate.Higher concentration self-adapted holes resulting from a vertical electric field are located in the spacing of two neighbouring n +-regions on the interface of a buried oxide layer,and therefore the electric field of a dielectric buried layer (E I) is enhanced by these holes effectively,leading to an improved breakdown voltage (BV).The V B and E I of the NCI P-channel LDMOS increase to-188 V and 502.3 V/μm from 75 V and 82.2 V/μm of the conventional P-channel LDMOS with the same thicknesses SOI layer and the buried oxide layer,respectively.The influences of structure parameters on the proposed device characteristics are investigated by simulation.Moreover,compared with the conventional device,the proposed device exhibits low special on-resistance.     

Improvement on the breakdown voltage for silicon-on-insulator devices based on epitaxy-separation by implantation oxygen by a partial buried n+-layer

A novel silicon-on-insulator (SOI) high-voltage device based on epitaxy-separation by implantation oxygen (SIMOX) with a partial buried n⁺-layer silicon-on-insulator (PBN SOI) is proposed in this paper. Based on the proposed expressions of the vertical interface electric field, the high concentration interface charges which are accumulated on the interface between top silicon layer and buried oxide layer (BOX) effectively enhance the electric field of the BOX (E_I), resulting in a high breakdown voltage (BV) for the device. For the same thicknesses of top silicon layer (10 μm) and BOX (0.375 upmum), the E_I and BV of PBN SOI are improved by 186.5% and 45.4% in comparison with those of the conventional SOI, respectively.     

具有纵向辅助耗尽衬底层的新型横向双扩散金属氧化物半导体场效应晶体管

为了优化横向双扩散金属氧化物半导体场效应晶体管(lateral double-diffused MOSFET,LDMOS)的击穿特性及器件性能,在传统LDMOS结构的基础上,提出了一种具有纵向辅助耗尽衬底层(assisted depletesubstrate layer,ADSL)的新型LDMOS.新加入的ADSL层使得漏端下方的纵向耗尽区大幅向衬底扩展,从而利用电场调制效应在ADSL层底部引入新的电场峰,使纵向电场得到优化,同时横向表面电场也因为电场调制效应而得到了优化.通过ISE仿真表明,当传统LDMOS与ADSL LDMOS的漂移区长度都是70μm时,击穿电压由462 V增大到897 V,提高了94%左右,并且优值也从0.55 MW/cm~2提升到1.24 MW/cm~2,提升了125%.因此,新结构ADSL LDMOS的器件性能较传统LDMOS有了极大的提升.进一步对ADSL层进行分区掺杂优化,在新结构的基础上,击穿电压在双分区时上升到938 V,三分区时为947 V.     

A uniform doping ultra-thin SOI LDMOS with accumulation-mode extended gate and back-side etching technology

A uniform doping ultra-thin silicon-on-insulator(SOI) lateral-double-diffused metal-oxide-semiconductor(LDMOS)with low specific on-resistance(R_on,sp) and high breakdown voltage(BV) is proposed and its mechanism is investigated.The proposed LDMOS features an accumulation-mode extended gate(AG) and back-side etching(BE). The extended gate consists of a P– region and two diodes in series. In the on-state with VGD 0, an electron accumulation layer is formed along the drift region surface under the AG. It provides an ultra-low resistance current path along the whole drift region surface and thus the novel device obtains a low temperature distribution. The R_on,sp is nearly independent of the doping concentration of the drift region. In the off-state, the AG not only modulates the surface electric field distribution and improves the BV, but also brings in a charge compensation effect to further reduce the R_on,sp. Moreover, the BE avoids vertical premature breakdown to obtain high BV and allows a uniform doping in the drift region, which avoids the variable lateral doping(VLD) and the "hot-spot" caused by the VLD. Compared with the VLD SOI LDMOS, the proposed device simultaneously reduces the R_on,sp by 70.2% and increases the BV from 776 V to 818 V.     

具有纵向漏极场板的低导通电阻绝缘体上硅横向双扩散金属氧化物半导体器件新结构

为降低绝缘体上硅(SOI)横向双扩散金属氧化物半导体(LDMOS)器件的导通电阻,同时提高器件击穿电压,提出了一种具有纵向漏极场板的低导通电阻槽栅槽漏SOI-LDMOS器件新结构.该结构特征为采用了槽栅槽漏结构,在纵向上扩展了电流传导区域,在横向上缩短了电流传导路径,降低了器件导通电阻;漏端采用了纵向漏极场板,该场板对漏端下方的电场进行了调制,从而减弱了漏极末端的高电场,提高了器件的击穿电压.利用二维数值仿真软件MEDICI对新结构与具有相同器件尺寸的传统SOI结构、槽栅SOI结构、槽栅槽漏SOI结构进行了比较.结果表明:在保证各自最高优值的条件下,与这三种结构相比,新结构的比导通电阻分别降低了53%,23%和提高了87%,击穿电压则分别提高了4%、降低了9%、提高了45%.比较四种结构的优值,具有纵向漏极场板的槽栅槽漏SOI结构优值最高,这表明在四种结构中新结构保持了较低导通电阻,同时又具有较高的击穿电压.     

Novel fast-switching LIGBT with P-buried layer and partial SOI

A novel silicon-on-insulator lateral insulated gate bipolar transistor(SOI LIGBT)is proposed in this paper.The proposed device has a P-type buried layer and a partial-SOI layer,which is called the BPSOI-LIGBT.Due to the electric field modulation effect generated by the P-type buried layer and the partial-SOI layer,the proposed structure generates two new peaks in the surface electric field distribution,which can achieve a smaller device size with a higher breakdown voltage.The smaller size of the device is beneficial to the fast switching.The simulation shows that under the same size,the breakdown voltage of the BPSOI LIGBT is 26%higher than that of the conventional partial-SOI LIGBT(PSOI LIGBT),and 84%higher than the traditional SOI LIGBT.When the forward voltage drop is 2.05 V,the turn-off time of the BPSOI LIGBT is 71%shorter than that of the traditional SOI LIGBT.Therefore,the proposed BPSOI LIGBT has a better forward voltage drop and turn-off time trade-off than the traditional SOI LIGBT.In addition,the BPSOI LIGBT effectively relieves the self-heating effect of the traditional SOI LIGBT.     

双面阶梯埋氧层部分SOI高压器件新结构

提出了双面阶梯埋氧层部分绝缘硅(silicon on insulator,SIO)高压器件新结构. 双面阶梯埋氧层的附加电场对表面电场的调制作用使表面电场达到近似理想的均匀分布, 耗尽层通过源极下硅窗口进一步向硅衬底扩展, 使埋氧层中纵向电场高达常规SOI结构的两倍, 且缓解了常规SOI结构的自热效应. 建立了漂移区电场的二维解析模型, 获得了器件结构参数间的优化关系. 结果表明, 在导通电阻相近的情况下, 双面阶梯埋氧层部分SOI结构击穿电压较常规SOI器件提高58％, 温度降低10—30K. 关键词： 双面阶梯 埋氧层 调制 自热效应     

Breakdown voltage model and structure realization of a thin silicon layer with linear variable doping on a silicon on insulator high voltage device with multiple step field plates

Based on the theoretical and experimental investigation of a thin silicon layer(TSL) with linear variable doping(LVD) and further research on the TSL LVD with a multiple step field plate(MSFP),a breakdown voltage(BV) model is proposed and experimentally verified in this paper.With the two-dimensional Poisson equation of the silicon on insulator(SOI) device,the lateral electric field in drift region of the thin silicon layer is assumed to be constant.For the SOI device with LVD in the thin silicon layer,the dependence of the BV on impurity concentration under the drain is investigated by an enhanced dielectric layer field(ENDIF),from which the reduced surface field(RESURF) condition is deduced.The drain in the centre of the device has a good self-isolation effect,but the problem of the high voltage interconnection(HVI) line will become serious.The two step field plates including the source field plate and gate field plate can be adopted to shield the HVI adverse effect on the device.Based on this model,the TSL LVD SOI n-channel lateral double-diffused MOSFET(nLDMOS) with MSFP is realized.The experimental breakdown voltage(BV) and specific on-resistance(R on,sp) of the TSL LVD SOI device are 694 V and 21.3 ·mm 2 with a drift region length of 60 μm,buried oxide layer of 3 μm,and silicon layer of 0.15 μm,respectively.     

阶梯氧化层新型折叠硅横向双扩散功率器件

为了设计功率集成电路所需的低功耗横向功率器件, 提出了一种具有阶梯氧化层折叠硅横向双扩散金属-氧化物-半导体(step oxide folding LDMOS, SOFLDMOS)新结构. 这种结构将阶梯氧化层覆盖在具有周期分布的折叠硅表面, 利用阶梯氧化层的电场调制效应, 通过在表面电场分布中引入新的电场峰而使表面电场分布均匀, 提高了器件的耐压范围, 解决了文献提出的折叠积累型横向双扩散金属-氧化物-半导体器件击穿电压受限的问题. 通过三维仿真软件ISE分析获得, SOFLDMOS 结构打破了硅的极限关系, 充分利用了电场调制效应、多数载流子积累和硅表面导电区倍增效应, 漏极饱和电流比一般LDMOS 提高3.4倍左右, 可以在62 V左右的反向击穿电压条件下, 获得0.74 mΩ·cm²超低的比导通电阻, 远低于传统LDMOS相同击穿电压下2.0 mΩ·cm²比导通电阻, 为实现低压功率集成电路对低功耗横向功率器件的要求提供了一种可选的方案.     

新型缓冲层分区电场调制横向双扩散超结功率器件

为了突破传统横向双扩散金属-氧化物-半导体器件(lateral double-diffused MOSFET)击穿电压与比导通电阻的极限关系,本文在缓冲层横向双扩散超结功率器件(super junction LDMOS-SJ LDMOS)结构基础上,提出了具有缓冲层分区新型SJ-LDMOS结构.新结构利用电场调制效应将分区缓冲层产生的电场峰引入超结(super junction)表面而优化了SJ-LDMOS的表面电场分布,缓解了横向LDMOS器件由于受纵向电场影响使横向电场分布不均匀、横向单位耐压量低的问题.利用仿真分析软件ISE分析表明,优化条件下,当缓冲层分区为3时,提出的缓冲层分区SJ-LDMOS表面电场最优,击穿电压达到饱和时较一般LDMOS结构提高了50%左右,较缓冲层SJ-LDMOS结构提高了32%左右,横向单位耐压量达到18.48 V/μm.击穿电压为382 V的缓冲层分区SJ-LDMOS,比导通电阻为25.6 mΩ·cm2,突破了一般LDMOS击穿电压为254 V时比导通电阻为71.8 mΩ·cm2的极限关系.     

A new analytical model of high voltage silicon on insulator （SOI） thin film devices

A new analytical model of high voltage silicon on insulator (SOI) thin film devices is proposed, and a formula of silicon critical electric field is derived as a function of silicon film thickness by solving a 2D Poisson equation from an effective ionization rate, with a threshold energy taken into account for electron multiplying. Unlike a conventional silicon critical electric field that is constant and independent of silicon film thickness, the proposed silicon critical electric field increases sharply with silicon film thickness decreasing especially in the case of thin films, and can come to 141V/μm at a film thickness of 0.1μm which is much larger than the normal value of about 30V/μm. From the proposed formula of silicon critical electric field, the expressions of dielectric layer electric field and vertical breakdown voltage (V_B,V) are obtained. Based on the model, an ultra thin film can be used to enhance dielectric layer electric field and so increase vertical breakdown voltage for SOI devices because of its high silicon critical electric field, and with a dielectric layer thickness of 2μm the vertical breakdown voltages reach 852 and 300V for the silicon film thicknesses of 0.1 and 5μm, respectively. In addition, a relation between dielectric layer thickness and silicon film thickness is obtained, indicating a minimum vertical breakdown voltage that should be avoided when an SOI device is designed. 2D simulated results and some experimental results are in good agreement with analytical results.