SiC based Si/SiC heterojunction and its rectifying characteristics

The Si on SiC heterojunction is still poorly understood, although it has a number of potential applications in electronic and optoelectronic devices, for example, light-activated SiC power switches where Si may play the role of an light absorbing layer. This paper reports on Si films heteroepitaxially grown on the Si face of (0001) n-type 6H-SiC substrates and the use of B₂H_6 as a dopant for p-Si grown at temperatures in a range of 700--950~\du. X-ray diffraction (XRD) analysis and transmission electron microscopy (TEM) tests have demonstrated that the samples prepared at the temperatures ranged from 850~℃ to 900~℃ are characterized as monocrystalline silicon. The rocking XRD curves show a well symmetry with FWHM of 0.4339° Omega. Twin crystals and stacking faults observed in the epitaxial layers might be responsible for widening of the rocking curves. Dependence of the crystal structure and surface topography on growth temperature is discussed based on the experimental results. The energy band structure and rectifying characteristics of the Si/SiC heterojunctions are also preliminarily tested.     

SiCGe/SiC 异质结及其光电特性的MEDICI 模拟

在对SiC1-xGex三元合金主要特性的研究基础上，利用器件仿真器MEDICI模拟和分析SiCGe/SiC异质结光电二极管的光电特性。计算表明， SiC1-xGex 在Ge组分为0.3时与3C-SiC晶格失配较小，此时的SiCGe/SiC异质结对可见光和近红外光有较好的光谱响应。当P型SiC1-xGex层杂质浓度为1×1015cm-3、厚度1.6μm、x=0.3时，SiC1-xGex /SiC异质结光电二极管对0.52μm可见光有250mA/W左右的响应度，对0.7μm近红外光也有102mA/W左右的响应度。     

Study of a 4H-SiC epitaxial n-channel MOSFET

Epitaxial channel metal-oxide semiconductor field-effect transistors (MOSFETs) have been proposed as one possible way to avoid the problem of low inversion layers in traditional MOSFETs. This paper presents an equation of maximum depletion width modified which is more accurate than the original equation. A 4H--SiC epitaxial n-channel MOSFET using two-dimensional simulator ISE is simulated. Optimized structure would be realized based on the simulated results for increasing channel mobility.     

High-mobility SiC MOSFET with low density of interface traps using high pressure microwave plasma oxidation

The microwave plasma oxidation under the relatively high pressure(6 kPa)region is introduced into the fabrication process of SiO2/4 H-SiC stack.By controlling the oxidation pressure,species,and temperature,the record low density of interface traps(~4×10¹⁰cm^-2·eV^-1@Ec-0.2 eV)is demonstrated on SiO2/SiC stack formed by microwave plasma oxidation.And high quality SiO2 with very flat interface(0.27-nm root-mean-square roughness)is obtained.High performance Si C metal–oxide–semiconductor field-effect transistors(MOSFETs)with peak field effect mobility of 44 cm^-2·eV^-1is realized without additional treatment.These results show the potential of a high-pressure plasma oxidation step for improving the channel mobility in SiC MOSFETs.     

Effect of energy distribution of interface states on the electrical characteristics of semiconductor heterojunction diode

An energy distribution of interface states has been considered to study the electrical characteristics of an anisotype semiconductor heterojunction. Various electrical quantities such as the surface potential, current, conductance and ideality factor of the device have been studied. The current-voltage and conductance-voltage characteristics are found largely sensitive to the parameters controlling the distribution profile of interface states. A new expression for the ideality factor of the device has been derived, which predicts appreciable voltage dependence due to the distributive nature of the interface states. It has been found that the experimental I-V data of p-InP/n-CdS heterojunction reported by earlier workers can be satisfactorily explained with the help of the present model if the effect of shunt resistance of the device is included in the evaluation scheme.     

1200 V碳化硅功率MOSFET低温特性的实验表征及分析

碳化硅功率MOSFET是宽禁带功率半导体器件的典型代表,具有优异的电气性能。基于低温环境下的应用需求,研究了1200 V碳化硅功率MOSFET在77.7 K至300 K温区的静/动态特性,定性分析了温度对碳化硅功率MOSFET性能的影响。实验结果显示,温度从300 K降低至77.7 K时,阈值电压上升177.24%,漏-源极击穿电压降低32.99%,栅极泄漏电流降低82.51%,导通电阻升高1142.28%,零栅压漏电流降低89.84%(300 K至125 K)。双脉冲测试显示,开通时间增大8.59%,关断时间降低16.86%,开关损耗增加48%。分析发现,碳化硅功率MOSFET较高的界面态密度和较差的沟道迁移率,是导致其在低温下性能劣化的主要原因。     

Sensitivity of heavy-ion-induced single event burnout in SiC MOSFET

The energy deposition and electrothermal behavior of SiC metal-oxide-semiconductor field-effect transistor(MOSFET)under heavy ion radiation are investigated based on Monte Carlo method and TCAD numerical simulation.The Monte Carlo simulation results show that the density of heavy ion-induced energy deposition is the largest in the center of the heavy ion track.The time for energy deposition in SiC is on the order of picoseconds.The TCAD is used to simulate the single event burnout(SEB)sensitivity of SiC MOSFET at four representative incident positions and four incident depths.When heavy ions strike vertically from SiC MOSFET source electrode,the SiC MOSFET has the shortest SEB time and the lowest SEB voltage with respect to direct strike from the epitaxial layer,strike from the channel,and strike from the body diode region.High current and strong electric field simultaneously appear in the local area of SiC MOSFET,resulting in excessive power dissipation,further leading to excessive high lattice temperature.The gate-source junction area and the substrate-epitaxial layer junction area are both the regions where the SiC lattice temperature first reaches the SEB critical temperature.In the SEB simulation of SiC MOSFET at different incident depths,when the incident depth does not exceed the device's epitaxial layer,the heavy-ion-induced charge deposition is not enough to make lattice temperature reach the SEB critical temperature.     

Improvement on short-circuit ability of SiC super-junction MOSFET with partially widened pillar structure

A novel 1200 V SiC super-junction (SJ) MOSFET with a partially widened pillar structure is proposed and investigated by using the two-dimensional numerical simulation tool. Based on the SiC SJ MOSFET structure, a partially widened P-region is added at the SJ pillar region to improve the short-circuit (SC) ability. After investigating the position and doping concentration of the widened P-region, an optimal structure is determined. From the simulation results, the SC withstand times (SCWTs) of the conventional trench MOSFET (CT-MOSFET), the SJ MOSFET, and the proposed structure at 800 V DC bus voltage are 15 μs, 17 μs, and 24 μs, respectively. The SCWTs of the proposed structure are increased by 60% and 41.2% in comparison with that of the other two structures. The main reason for the proposed structure with an enhanced SC capability is related to the effective suppression of saturation current at the high DC bias conditions by using a modulated P-pillar region. Meanwhile, a good Baliga's FOM ($BV^{2}/R_{rm on}$) also can be achieved in the proposed structure due to the advantage of the SJ structure. In addition, the fabrication technology of the proposed structure is compatible with the standard epitaxy growth method used in the SJ MOSFET. As a result, the SJ structure with this feasible optimization skill presents an effect on improving the SC reliability of the SiC SJ MOSFET without the degeneration of the Baliga's FOM.     

基于场效应管与阶跃恢复二极管的皮秒级脉冲源设计

针对已有脉冲源无法兼顾脉冲宽度和幅值的现象,提出一种基于场效应管（MOSFET）和阶跃恢复二极管（SRD）相结合的皮秒级脉冲源设计方案。通过研究分析传统的几种脉冲源的设计方案,设计出一种百伏级的高重频皮秒级脉冲发生器,在PSPICE上对设计方案进行仿真并制作出脉冲源PCB板,实测在2 MHz的重频下产生半幅脉宽约为400 ps、幅度110 V以上的极窄脉冲,波形稳定,为高分辨的超宽带探测雷达发射机的设计提供了新的选择方案。     

A novel type of ultra fast and ultra soft recovery SiGe/Si heterojunction power diode with an ideal ohmic contact

A novel type of p^+(SiGe)－n^-－n^+ heterojunction switching power diode with high-speed capability is presented to overcome the drawbacks of existing power diodes. The improvement is achieved by using a p^+－n^+ mosaic layer as a substitute for the n^+ region in the conventional p^+(SiGe)－n^-－n^+ diode to realize an `ideal ohmic' contact for electrons and holes simultaneously. Compared with conventional p^+(SiGe)－n^-－n^+ diodes, the ideal ohmic contact p^+(SiGe)－n^-－n^+ diodes have about one third of the reverse recovery time and a half of peak reverse recovery current. Furthermore, the softness factor increases nearly two times and the leakage current decreases 1－2 orders of magnitude. These improvements are achieved without resorting special process step to lower the carrier lifetime and thus the devices could be easily integrated into power ICs. The Ge percentage content of p^+(SiGe) layer is an important parameter for the optimal device design.     

Optically controlled SiCGe/SiC heterojunction transistor with charge-compensation layer

A novel optically controlled SiCGe/SiC heterojunction transistor with charge-compensation technique has been simulated by using commercial simulator.This paper discusses the electric field distribution,spectral response and transient response of the device.Due to utilizing p-SiCGe charge-compensation layer,the responsivity increases nearly two times and breakdown voltage increases 33%.The switching characteristic illustrates that the device is latch-free and its fall time is much longer than the rise time.With an increase of the light power density and wavelength,the rise time and fall time will become shorter and longer,respectively.In terms of carrier lifetime,a compromise should be made between the responsivity and switching speed,the ratio of them reaches maximum value when the minority carrier lifetime equals 90 ns.     

A novel superjunction MOSFET with improved ruggedness under unclamped inductive switching

The ruggedness of a superjunction metal–oxide semiconductor field-effect transistor (MOSFET) under unclamped inductive switching conditions is improved by optimizing the avalanche current path. Inserting a P-island with relatively high doping concentration into the P-column, the avalanche breakdown point is localized. In addition, a trench type P+ contact is designed to shorten the current path. As a consequence, the avalanche current path is located away from the N+ source/P-body junction and the activation of the parasitic transistor can be effectively avoided. To verify the proposed structural mechanism, a two-dimensional (2D) numerical simulation is performed to describe its static and on-state avalanche behaviours, and a method of mixed-mode device and circuit simulation is used to predict its performances under realistic unclamped inductive switching. Simulation shows that the proposed structure can endure a remarkably higher avalanche energy compared with a conventional superjunction MOSFET.     

Comparison of fibre/matrix interface strength for a 3D woven SiC/SiC composite

The fibre/matrix interface shear strength, τ _P, was determined by analysis of fibre pullout length distributions for a 3D woven SiC/SiC-based composite that had undergone tensile testing between room temperature and 1300°C in vacuum and air. Data was compared with the fibre/matrix interface shear strength, τ _S, obtained previously for this system by analysis of in situ fibre strength distributions. τ _P was found to follow the same general trend as that of τ _S and this was explained in terms of the carbon-rich fibre/matrix interface region. However, τ _P was smaller than τ _S by a factor of 3-4 for all cases, but the reason for this remains unclear although several tentative suggestions have been put forward.     

The fabrication and photoresponse of ZnO/diamond film heterojunction diode

Boron-doped p-type freestanding diamond (FSD) films were prepared by hot filament chemical vapor deposition (HFCVD) method. The effect of B/C ratio on the electrical properties of FSD films was investigated by Hall effect measurement system. A ZnO/diamond heterojunction diode was fabricated successfully by depositing n-type ZnO films on the p-type FSD substrate by radio-frequency (RF) magnetron sputtering method. The wavelength dependent photoresponse properties of the heterojunction diode were investigated by studying the effect of light illumination on current-voltage (I-V) characteristics and photocurrent spectra at room temperature. The diode showed a significant discrimination between ultraviolet (UV) and the visible light under reverse bias conditions and photoresponse of the device was approximately linear related to the increasing reverse bias voltages.     

Electronic and photovoltaic properties of p-Si/C70 heterojunction diode

Electronic and photovoltaic properties of p-Si/C₇₀ heterojunction diode have been investigated. The ideality factor n and barrier height φ_b values of the diode were found to be 1.86 and 0.69 eV, respectively. The diode indicates a non-ideal current–voltage behaviour due to the ideality factor being higher than unity. This behaviour results from the effect of series resistance and the presence of an interfacial layer. The series resistance R_S and ideality factor n values were determined using Cheng's method and the obtained values are 2.21×10⁵ Ω and 1.86, respectively. The device shows photovoltaic behaviour with a maximum open-circuit voltage of 0.22 V and a short-circuit current of 0.35 μA under 6 mW/cm² light intensity.     

MEH-PPV/Alq_3-based bulk heterojunction photodetector

In this paper, we present the effect of varied illumination levels on the electrical properties of the organic blend bulk heterojuction （BHJ） photodiode. To prepare the BHJ blend, poly（2-methoxy-5（2P-ethylhexyloxy） phenyleneviny- lene （MEH-PPV） and aluminum-tris-（8-hydroxyquinoline） （Alq3） are used as donor and acceptor materials, respectively. In order to fabricate the photodiode, a 40-nm thick film of poly（3, 4-ethylendioxytbiophene）：poly（styrensulfonate） （PE- DOT：PSS） is primarily deposited on a cleaned ITO coated glass substrate by spin coating technique. The organic photo- sensitive blend is later spun coated on the PEDOT：PSS layer, followed by the lithium fluoride （LiF） and aluminium （A1） thin films deposition by thermal evaporation. The optical properties of the MEH-PPV：Alq3 blend thin films are investigated using photoluminescence （PL） and UV-Vis spectroscopy. The photodiode shows good photo-current response as a function of variable illumination levels. The responsivity value - 8 mA/W at 3 V is found and the ratio of photo-current to dark current （lph/IDark） is found to be 1.24.     

CVD法制备p-ZnO薄膜/n-Si异质结发光二极管及其性能研究

利用简单的化学气相沉积方法, 首先在n-Si衬底上生长Sb掺杂p-ZnO薄膜, 并在此基础上制作了p-ZnO/n-Si异质结发光二极管．对制备的Sb掺杂ZnO薄膜 在800 ℃下进行了热退火处理, 发现退火后样品的晶体质量和表面形貌都得到明显提高, 并且薄膜呈现的电导类型为p型, 载流子浓度为9.56× 10¹⁷ cm^-3. 此外, 该器件还表现出良好的整流特性, 正向开启电压为4.0 V, 反向击穿电压为9.5 V. 在正向45 mA的注入电流条件下, 器件实现了室温下的电致发光. 这说明较高质量的ZnO薄膜也可以通过简单的化学气相沉积方法来实现, 这为ZnO基光电器件的材料制备提供了一种简单可行的方法. 关键词： CVD p-ZnO 异质结 电致发光     

Influence of growth temperature and post-annealing on an n-ZnO/p-GaN heterojunction diode

We report on an n-ZnO/p-GaN heterojunction diode fabricated from zinc oxide (ZnO) films at various growth temperatures (450, 500, 550, and 600 °C) by RF sputtering. The films were subsequently annealed at 700 °C in N₂ ambient. To investigate the influence of the growth temperature of n-ZnO films, the microstructural, optical, and electrical properties were measured using scanning electron microscopy (SEM), X-ray diffraction (XRD), photoluminescence (PL), and Hall measurements. The XRD pattern showed the preferred orientation along the c-axis (002) regardless of growth temperature. The PL spectra showed a dominant sharp near-band-edge (NBE) emission. Current–voltage (I–V) curves showed excellent rectification behavior. The turn-on voltage of the diode was observed to be 3.2 V for the films produced at 500 °C. The ideality factor of ZnO film was observed to be 1.37, which showed the best performance of the diode.     

Ultraviolet electroluminescence from ZnO-based light-emitting diode with p-ZnO:N/n-GaN:Si heterojunction structure

A p-ZnO:N/n-GaN:Si structure heterojunction light-emitting diode (LED) is fabricated on c-plane sapphire by full metal organic chemical vapor deposition (MOCVD) technique. The p-type layer with hole concentration of 8.94×10¹⁶ cm⁻³ is composed of nitrogen-doped ZnO using NH₃ as the doping source with subsequent annealing in N₂O plasma ambient. Silicon-doped GaN film with electron concentration of 1.15×10¹⁸ cm⁻³ is used as the n-type layer. Desirable rectifying behavior is observed from the current-voltage (I-V) curve of the device. The forward turn on voltage is about 4 V and the reverse breakdown voltage is more than 7 V. A distinct ultraviolet (UV) electroluminescence (EL) with a dominant emission peak centered at 390 nm is detected at room temperature from the heterojunction structure under forward bias conditions. The origins of the EL emissions are discussed in comparison with the photoluminescence (PL) spectra.     

A super junction SiGe low-loss fast switching power diode

This paper proposes a novel super junction (SJ) SiGe switching power diode which has a columnar structure of alternating p^- and n^- doped pillar substituting conventional n^- base region and has far thinner strained SiGe p⁺ layer to overcome the drawbacks of existing Si switching power diode. The SJ SiGe diode can achieve low specific on-resistance, high breakdown voltages and fast switching speed. The results indicate that the forward voltage drop of SJ SiGe diode is much lower than that of conventional Si power diode when the operating current densities do not exceed 1000 A/cm², which is very good for getting lower operating loss. The forward voltage drop of the Si diode is 0.66V whereas that of the SJ SiGe diode is only 0.52 V at operating current density of 10 A/cm². The breakdown voltages are 203 V for the former and 235 V for the latter. Compared with the conventional Si power diode, the reverse recovery time of SJ SiGe diode with 20 per cent Ge content is shortened by above a half and the peak reverse current is reduced by over 15%. The SJ SiGe diode can remarkably improve the characteristics of power diode by combining the merits of both SJ structure and SiGe material.