Partial-SOI high voltage P-channel LDMOS with interface accumulation holes

A new partial SOI (silion-on-insulator) (PSOI) high voltage P-channel LDMOS (lateral double-diffused metal-oxide semiconductor) with an interface hole islands (HI) layer is proposed and its breakdown characteristics are investigated theoretically. A high concentration of charges accumulate on the interface, whose density changes with the negative drain voltage, which increase the electric field (E_I) in the dielectric buried oxide layer (BOX) and modulate the electric field in drift region . This results in the enhancement of the breakdown voltage (BV). The values of E_I and BV of an HI PSOI with a 2-μm thick SOI layer over a 1-μm thick buried layer are 580V/μm and -582 V, respectively, compared with 81.5 V/μm and -123 V of a conventional PSOI. Furthermore, the Si window also alleviates the self-heating effect (SHE). Moreover, in comparison with the conventional device, the proposed device exhibits low on-resistance.     

Compound buried layer SOI high voltage device with a step buried oxide

A silicon-on-insulator (SOI) high performance lateral double-diffusion metal oxide semiconductor (LDMOS) on a compound buried layer (CBL) with a step buried oxide (SBO CBL SOI) is proposed.The step buried oxide locates holes in the top interface of the upper buried oxide (UBO) layer.Furthermore,holes with high density are collected in the interface between the polysilicon layer and the lower buried oxide (LBO) layer.Consequently,the electric fields in both the thin LBO and the thick UBO are enhanced by these holes,leading to an improved breakdown voltage.The breakdown voltage of the SBO CBL SOI LDMOS increases to 847 V from the 477 V of a conventional SOI with the same thicknesses of SOI layer and the buried oxide layer.Moreover,SBO CBL SOI can also reduce the self-heating effect.     

A new analytical model for the surface electric field distribution and breakdown voltage of the SOI trench LDMOS

A new analytical model for the surface electric field distribution and breakdown voltage of the silicon on insulator (SOI) trench lateral double-diffused metal-oxide-semiconductor (LDMOS) is presented. Based on the two-dimensional Laplace solution and Poisson solution, the model considers the influence of structure parameters such as the doping concentration of the drift region, and the depth and width of the trench on the surface electric field. Further, a simple analytical expression of the breakdown voltage is obtained, which offers an effective way to gain an optimal high voltage. All the analytical results are in good agreement with the simulation results.     

Partial-SOI high voltage laterally double-diffused MOS with a partially buried n~+-layer

A novel partial silicon-on-insulator laterally double-diffused metal-oxide-semiconductor transistor （PSOI LDMOS） with a thin buried oxide layer is proposed in this paper. The key structure feature of the device is an n＋-layer, which is partially buried on the bottom interface of the top silicon layer （PBNL PSOI LDMOS）. The undepleted interface n＋-layer leads to plenty of positive charges accumulated on the interface, which will modulate the distributions of the lateral and vertical electric fields for the device, resulting in a high breakdown voltage （BV）. With the same thickness values of the top silicon layer （10 p.m） and buried oxide layer （0.375 μm）, the BV of the PBNL PSOI LDMOS increases to 432 V from 285 V of the conventional PSOI LDMOS, which is improved by 51.6%.     

A new analytical model of high voltage silicon on insulator （SOI） thin film devices

A new analytical model of high voltage silicon on insulator (SOI) thin film devices is proposed, and a formula of silicon critical electric field is derived as a function of silicon film thickness by solving a 2D Poisson equation from an effective ionization rate, with a threshold energy taken into account for electron multiplying. Unlike a conventional silicon critical electric field that is constant and independent of silicon film thickness, the proposed silicon critical electric field increases sharply with silicon film thickness decreasing especially in the case of thin films, and can come to 141V/μm at a film thickness of 0.1μm which is much larger than the normal value of about 30V/μm. From the proposed formula of silicon critical electric field, the expressions of dielectric layer electric field and vertical breakdown voltage (V_B,V) are obtained. Based on the model, an ultra thin film can be used to enhance dielectric layer electric field and so increase vertical breakdown voltage for SOI devices because of its high silicon critical electric field, and with a dielectric layer thickness of 2μm the vertical breakdown voltages reach 852 and 300V for the silicon film thicknesses of 0.1 and 5μm, respectively. In addition, a relation between dielectric layer thickness and silicon film thickness is obtained, indicating a minimum vertical breakdown voltage that should be avoided when an SOI device is designed. 2D simulated results and some experimental results are in good agreement with analytical results.     

An analytical model for the vertical electric field distribution and optimization of high voltage REBULF LDMOS

In this paper, an analytical model for the vertical electric field distribution and optimization of a high voltage-reduced bulk field(REBULF) lateral double-diffused metal–oxide-semiconductor(LDMOS) transistor is presented. The dependences of the breakdown voltage on the buried n-layer depth, thickness, and doping concentration are discussed in detail.The REBULF criterion and the optimal vertical electric field distribution condition are derived on the basis of the optimization of the electric field distribution. The breakdown voltage of the REBULF LDMOS transistor is always higher than that of a single reduced surface field(RESURF) LDMOS transistor, and both analytical and numerical results show that it is better to make a thick n-layer buried deep into the p-substrate.     

Non-depletion floating layer in SOI LDMOS for enhancing breakdown voltage and eliminating back-gate bias effect

A non-depletion floating layer silicon-on-insulator (NFL SOI) lateral double-diffused metal-oxide-semiconductor (LDMOS) is proposed and the NFL-assisted modulated field (NFLAMF) principle is investigated in this paper. Based on this principle, the floating layer can pin the potential for modulating bulk field. In particular, the accumulated high concentration of holes at the bottom of the NFL can efficiently shield the electric field of the SOI layer and enhance the dielectric field in the buried oxide layer (BOX). At variation of back-gate bias, the shielding charges of NFL can also eliminate back-gate effects. The simulated results indicate that the breakdown voltage (BV) is increased from 315 V to 558 V compared to the conventional reduced surface field (RESURF) SOI (CSOI) LDMOS, yielding a 77% improvement. Furthermore, due to the field shielding effect of the NFL, the device can maintain the same breakdown voltage of 558 V with a thinner BOX to resolve the thermal problem in an SOI device.     

具有L型源极场板的双槽绝缘体上硅高压器件新结构

为了提高小尺寸绝缘体上硅(SOI)器件的击穿电压,同时降低器件比导通电阻,提出了一种具有L型源极场板的双槽SOI高压器件新结构.该结构具有如下特征:首先,采用了槽栅结构,使电流纵向传导面积加宽,降低了器件的比导通电阻;其次,在漂移区引入了Si O2槽型介质层,该介质层的高电场使器件的击穿电压显著提高;第三,在槽型介质层中引入了L型源极场板,该场板调制了漂移区电场,使优化漂移区掺杂浓度大幅增加,降低了器件的比导通电阻.二维数值仿真结果表明:与传统SOI结构相比,在相同器件尺寸时,新结构的击穿电压提高了151%,比导通电阻降低了20%;在相同击穿电压时,比导通电阻降低了80%.与相同器件尺寸的双槽SOI结构相比,新结构保持了双槽SOI结构的高击穿电压特性,同时,比导通电阻降低了26%.     

Improvement on the breakdown voltage for silicon-on-insulator devices based on epitaxy-separation by implantation oxygen by a partial buried n~+-layer

A novel silicon-on-insulator (SOI) high-voltage device based on epitaxy-separation by implantation oxygen (SIMOX) with a partial buried n +-layer silicon-on-insulator (PBN SOI) is proposed in this paper.Based on the proposed expressions of the vertical interface electric field,the high concentration interface charges which are accumulated on the interface between top silicon layer and buried oxide layer (BOX) effectively enhance the electric field of the BOX (E_I),resulting in a high breakdown voltage (BV) for the device.For the same thicknesses of top silicon layer (10 μm) and BOX (0.375 μm),the E I and BV of PBN SOI are improved by 186.5% and 45.4% in comparison with those of the conventional SOI,respectively.     

Breakdown voltage model and structure realization of a thin silicon layer with linear variable doping on a silicon on insulator high voltage device with multiple step field plates

Based on the theoretical and experimental investigation of a thin silicon layer(TSL) with linear variable doping(LVD) and further research on the TSL LVD with a multiple step field plate(MSFP),a breakdown voltage(BV) model is proposed and experimentally verified in this paper.With the two-dimensional Poisson equation of the silicon on insulator(SOI) device,the lateral electric field in drift region of the thin silicon layer is assumed to be constant.For the SOI device with LVD in the thin silicon layer,the dependence of the BV on impurity concentration under the drain is investigated by an enhanced dielectric layer field(ENDIF),from which the reduced surface field(RESURF) condition is deduced.The drain in the centre of the device has a good self-isolation effect,but the problem of the high voltage interconnection(HVI) line will become serious.The two step field plates including the source field plate and gate field plate can be adopted to shield the HVI adverse effect on the device.Based on this model,the TSL LVD SOI n-channel lateral double-diffused MOSFET(nLDMOS) with MSFP is realized.The experimental breakdown voltage(BV) and specific on-resistance(R on,sp) of the TSL LVD SOI device are 694 V and 21.3 ·mm 2 with a drift region length of 60 μm,buried oxide layer of 3 μm,and silicon layer of 0.15 μm,respectively.     

Improvement on the breakdown voltage for silicon-on-insulator devices based on epitaxy-separation by implantation oxygen by a partial buried n+-layer

A novel silicon-on-insulator (SOI) high-voltage device based on epitaxy-separation by implantation oxygen (SIMOX) with a partial buried n⁺-layer silicon-on-insulator (PBN SOI) is proposed in this paper. Based on the proposed expressions of the vertical interface electric field, the high concentration interface charges which are accumulated on the interface between top silicon layer and buried oxide layer (BOX) effectively enhance the electric field of the BOX (E_I), resulting in a high breakdown voltage (BV) for the device. For the same thicknesses of top silicon layer (10 μm) and BOX (0.375 upmum), the E_I and BV of PBN SOI are improved by 186.5% and 45.4% in comparison with those of the conventional SOI, respectively.     

Modeling of high permittivity insulator structure with interface charge by charge compensation

An analytical model of the power metal–oxide–semiconductor field-effect transistor(MOSFET)with high permittivity insulator structure(HKMOS)with interface charge is established based on superposition and developed for optimization by charge compensation.In light of charge compensation,the disturbance aroused by interface charge is efficiently compromised by introducing extra charge for maximizing breakdown voltage(BV)and minimizing specific ON-resistance(R_on,sp).From this optimization method,it is very efficient to obtain the design parameters to overcome the difficulty in implementing the R_on,sp–BV trade-off for quick design.The analytical results prove that in the HKMOS with positive or negative interface charge at a given length of drift region,the extraction of the parameters is qualitatively and quantitatively optimized for trading off BV and Ron,sp with JFET effect taken into account.     

Design optimization of high breakdown voltage vertical GaN junction barrier Schottky diode with high-K/low-K compound dielectric structure

A vertical junction barrier Schottky diode with a high-$K$/low-$K$ compound dielectric structure is proposed and optimized to achieve a high breakdown voltage (BV). There is a discontinuity of the electric field at the interface of high-$K$ and low-$K$ layers due to the different dielectric constants of high-$K$ and low-$K$ dielectric layers. A new electric field peak is introduced in the n-type drift region of junction barrier Schottky diode (JBS), so the distribution of electric field in JBS becomes more uniform. At the same time, the effect of electric-power line concentration at the p-n junction interface is suppressed due to the effects of the high-$K$ dielectric layer and an enhancement of breakdown voltage can be achieved. Numerical simulations demonstrate that GaN JBS with a specific on-resistance ($R_{\rm on, sp}$) of 2.07 m$\Omega\cdot$cm$^{2}$ and a BV of 4171 V which is 167% higher than the breakdown voltage of the common structure, resulting in a high figure-of-merit (FOM) of 8.6 GW/cm$^{2}$, and a low turn-on voltage of 0.6 V.     

双面阶梯埋氧层部分SOI高压器件新结构

提出了双面阶梯埋氧层部分绝缘硅(silicon on insulator,SIO)高压器件新结构. 双面阶梯埋氧层的附加电场对表面电场的调制作用使表面电场达到近似理想的均匀分布, 耗尽层通过源极下硅窗口进一步向硅衬底扩展, 使埋氧层中纵向电场高达常规SOI结构的两倍, 且缓解了常规SOI结构的自热效应. 建立了漂移区电场的二维解析模型, 获得了器件结构参数间的优化关系. 结果表明, 在导通电阻相近的情况下, 双面阶梯埋氧层部分SOI结构击穿电压较常规SOI器件提高58％, 温度降低10—30K. 关键词： 双面阶梯 埋氧层 调制 自热效应     

具有纵向漏极场板的低导通电阻绝缘体上硅横向双扩散金属氧化物半导体器件新结构

为降低绝缘体上硅(SOI)横向双扩散金属氧化物半导体(LDMOS)器件的导通电阻,同时提高器件击穿电压,提出了一种具有纵向漏极场板的低导通电阻槽栅槽漏SOI-LDMOS器件新结构.该结构特征为采用了槽栅槽漏结构,在纵向上扩展了电流传导区域,在横向上缩短了电流传导路径,降低了器件导通电阻;漏端采用了纵向漏极场板,该场板对漏端下方的电场进行了调制,从而减弱了漏极末端的高电场,提高了器件的击穿电压.利用二维数值仿真软件MEDICI对新结构与具有相同器件尺寸的传统SOI结构、槽栅SOI结构、槽栅槽漏SOI结构进行了比较.结果表明:在保证各自最高优值的条件下,与这三种结构相比,新结构的比导通电阻分别降低了53%,23%和提高了87%,击穿电压则分别提高了4%、降低了9%、提高了45%.比较四种结构的优值,具有纵向漏极场板的槽栅槽漏SOI结构优值最高,这表明在四种结构中新结构保持了较低导通电阻,同时又具有较高的击穿电压.     

A novel analytical thermal model for multilevel nano-scale interconnects considering the via effect

Based on the heat diffusion equation of multilevel interconnects, a novel analytical thermal model for multilevel nano-scale interconnects considering the via effect is presented, which can compute quickly the temperature of multilevel interconnects, with substrate temperature given. Based on the proposed model and the 65~nm complementary metal oxide semiconductor (CMOS) process parameter, the temperature of nano-scale interconnects is computed. The computed results show that the via effect has a great effect on local interconnects, but the reduction of thermal conductivity has little effect on local interconnects. With the reduction of thermal conductivity or the increase of current density, however, the temperature of global interconnects rises greatly, which can result in a great deterioration in their performance. The proposed model can be applied to computer aided design (CAD) of very large-scale integrated circuits (VLSIs) in nano-scale technologies.     

An AlGaN/GaN HEMT with a reduced surface electric field and an improved breakdown voltage

A reduced surface electric field in an AlGaN/GaN high electron mobility transistor(HEMT) is investigated by employing a localized Mg-doped layer under the two-dimensional electron gas(2-DEG) channel as an electric field shaping layer.The electric field strength around the gate edge is effectively relieved and the surface electric field is distributed evenly as compared with those of HEMTs with conventional source-connected field plate and double field plate structures with the same device physical dimensions.Compared with the HEMTs with conventional sourceconnected field plates and double field plates,the HEMT with a Mg-doped layer also shows that the breakdown location shifts from the surface of the gate edge to the bulk Mg-doped layer edge.By optimizing both the length of Mg-doped layer,L m,and the doping concentration,a 5.5 times and 3 times the reduction in the peak electric field near the drain side gate edge is observed as compared with those of the HEMTs with source-connected field plate structure and double field plate structure,respectively.In a device with V GS = -5 V,L m = 1.5 μm,a peak Mg doping concentration of 8×10 17cm-3 and a drift region length of 10 μm,the breakdown voltage is observed to increase from 560 V in a conventional device without field plate structure to over 900 V without any area overhead penalty.     

新型高速半导体器件IMOS阈值电压解析模型

本文在研究IMOS器件结构的基础上, 分析了该器件不同区域的表面电场, 结合雪崩击穿条件, 建立了P-IMOS的阈值电压解析模型. 应用MATLAB对该器件阈值电压模型与源漏电压、栅长和硅层厚度的关系进行了数值分析, 并用二维器件仿真工具ISE进行了验证. 结果表明, 源电压越大, 阈值电压值越小; 栅长所占比例越大, 阈值电压值越小, 硅层厚度越小, 阈值电压值越小. 本文提出的模型与ISE仿真结果一致, 也与文献报道符合. 这种新型高速半导体器件IMOS阈值电压解析模型的建立为该高性能器件及对应电路的设计、仿真和制造提供了重要的参考.     

A novel 4H-SiC lateral bipolar junction transistor structure with high voltage and high current gain

In this paper, a novel structure of a 4H-SiC lateral bipolar junction transistor (LBJT) with a base field plate and double RESURF in the drift region is presented. Collector-base junction depletion extension in the base region is restricted by the base field plate. Thin base as well as low base doping of the LBJT therefore can be achieved under the condition of avalanche breakdown. Simulation results show that thin base of 0.32 μm and base doping of 3×1017 cm-3 are obtained, and corresponding current gain is as high as 247 with avalanche breakdown voltage of 3309 V when the drift region length is 30 μm. Besides, an investigation of a 4H-SiC vertical BJT (VBJT) with comparable breakdown voltage (3357 V) shows that the minimum base width of 0.25 μm and base doping as high as 8×1017 cm-3 contribute to a maximum current gain of only 128.