A-188 V 7.2Ω·mm~2,P-channel high voltage device formed on an epitaxy-SIMOX substrate

This paper proposes a new n +-charge island (NCI) P-channel lateral double diffused metal-oxide semiconductor (LDMOS) based on silicon epitaxial separation by implantation oxygen (E-SIMOX) substrate.Higher concentration self-adapted holes resulting from a vertical electric field are located in the spacing of two neighbouring n +-regions on the interface of a buried oxide layer,and therefore the electric field of a dielectric buried layer (E I) is enhanced by these holes effectively,leading to an improved breakdown voltage (BV).The V B and E I of the NCI P-channel LDMOS increase to-188 V and 502.3 V/μm from 75 V and 82.2 V/μm of the conventional P-channel LDMOS with the same thicknesses SOI layer and the buried oxide layer,respectively.The influences of structure parameters on the proposed device characteristics are investigated by simulation.Moreover,compared with the conventional device,the proposed device exhibits low special on-resistance.     

Partial-SOI high voltage P-channel LDMOS with interface accumulation holes

A new partial SOI (silion-on-insulator) (PSOI) high voltage P-channel LDMOS (lateral double-diffused metal-oxide semiconductor) with an interface hole islands (HI) layer is proposed and its breakdown characteristics are investigated theoretically. A high concentration of charges accumulate on the interface, whose density changes with the negative drain voltage, which increase the electric field (E_I) in the dielectric buried oxide layer (BOX) and modulate the electric field in drift region . This results in the enhancement of the breakdown voltage (BV). The values of E_I and BV of an HI PSOI with a 2-μm thick SOI layer over a 1-μm thick buried layer are 580V/μm and -582 V, respectively, compared with 81.5 V/μm and -123 V of a conventional PSOI. Furthermore, the Si window also alleviates the self-heating effect (SHE). Moreover, in comparison with the conventional device, the proposed device exhibits low on-resistance.     

Improvement on the breakdown voltage for silicon-on-insulator devices based on epitaxy-separation by implantation oxygen by a partial buried n+-layer

A novel silicon-on-insulator (SOI) high-voltage device based on epitaxy-separation by implantation oxygen (SIMOX) with a partial buried n⁺-layer silicon-on-insulator (PBN SOI) is proposed in this paper. Based on the proposed expressions of the vertical interface electric field, the high concentration interface charges which are accumulated on the interface between top silicon layer and buried oxide layer (BOX) effectively enhance the electric field of the BOX (E_I), resulting in a high breakdown voltage (BV) for the device. For the same thicknesses of top silicon layer (10 μm) and BOX (0.375 upmum), the E_I and BV of PBN SOI are improved by 186.5% and 45.4% in comparison with those of the conventional SOI, respectively.     

A novel partial silicon on insulator high voltage LDMOS with low-k dielectric buried layer

A novel partial silicon-on-insulator (PSOI) high voltage device with a low-k (relative permittivity) dielectric buried layer (LK PSOI) and its breakdown mechanism are presented and investigated by MEDICI.At a low k value the electric field strength in the dielectric buried layer (E I) is enhanced and a Si window makes the substrate share the vertical drop,resulting in a high vertical breakdown voltage;in the lateral direction,a high electric field peak is introduced at the Si window,which modulates the electric field distribution in the SOI layer;consequently,a high breakdown voltage (BV) is obtained.The values of EI and BV of LK PSOI with kI=2 on a 2 μm thick SOI layer over 1 μm thick buried layer are enhanced by 74% and 19%,respectively,compared with those of the conventional PSOI.Furthermore,the Si window also alleviates the self-heating effect.     

Novel high-voltage power lateral MOSFET with adaptive buried electrodes

A new high-voltage and low-specific on-resistance (R on,sp ) adaptive buried electrode (ABE) silicon-on-insulator (SOI) power lateral MOSFET and its analytical model of the electric fields are proposed. The MOSFET features are that the electrodes are in the buried oxide (BOX) layer, the negative drain voltage V d is divided into many partial voltages and the output to the electrodes is in the buried oxide layer and the potentials on the electrodes change linearly from the drain to the source. Because the interface silicon layer potentials are lower than the neighboring electrode potentials, the electronic potential wells are formed above the electrode regions, and the hole potential wells are formed in the spacing of two neighbouring electrode regions. The interface hole concentration is much higher than the electron concentration through designing the buried layer electrode potentials. Based on the interface charge enhanced dielectric layer field theory, the electric field strength in the buried layer is enhanced. The vertical electric field E I and the breakdown voltage (BV) of ABE SOI are 545 V/μm and -587 V in the 50 μm long drift region and the 1 μm thick dielectric layer, and a low R on,sp is obtained. Furthermore, the structure also alleviates the self-heating effect (SHE). The analytical model matches the simulation results.     

Novel high-voltage power device based on self-adaptive interface charge

This paper presents a novel high-voltage lateral double diffused metal--oxide semiconductor (LDMOS) with self-adaptive interface charge (SAC) layer and its physical model of the vertical interface electric field. The SAC can be self-adaptive to collect high concentration dynamic inversion holes, which effectively enhance the electric field of dielectric buried layer (E_I) and increase breakdown voltage (BV). The BV and E_I of SAC LDMOS increase to 612 V and 600 V/μm from 204 V and 90.7 V/μm of the conventional silicon-on-insulator, respectively. Moreover, enhancement factors of η which present the enhanced ability of interface charge on E_I are defined and analysed.     

双面阶梯埋氧层部分SOI高压器件新结构

提出了双面阶梯埋氧层部分绝缘硅(silicon on insulator,SIO)高压器件新结构. 双面阶梯埋氧层的附加电场对表面电场的调制作用使表面电场达到近似理想的均匀分布, 耗尽层通过源极下硅窗口进一步向硅衬底扩展, 使埋氧层中纵向电场高达常规SOI结构的两倍, 且缓解了常规SOI结构的自热效应. 建立了漂移区电场的二维解析模型, 获得了器件结构参数间的优化关系. 结果表明, 在导通电阻相近的情况下, 双面阶梯埋氧层部分SOI结构击穿电压较常规SOI器件提高58％, 温度降低10—30K. 关键词： 双面阶梯 埋氧层 调制 自热效应     

Breakdown voltage model and structure realization of a thin silicon layer with linear variable doping on a silicon on insulator high voltage device with multiple step field plates

Based on the theoretical and experimental investigation of a thin silicon layer(TSL) with linear variable doping(LVD) and further research on the TSL LVD with a multiple step field plate(MSFP),a breakdown voltage(BV) model is proposed and experimentally verified in this paper.With the two-dimensional Poisson equation of the silicon on insulator(SOI) device,the lateral electric field in drift region of the thin silicon layer is assumed to be constant.For the SOI device with LVD in the thin silicon layer,the dependence of the BV on impurity concentration under the drain is investigated by an enhanced dielectric layer field(ENDIF),from which the reduced surface field(RESURF) condition is deduced.The drain in the centre of the device has a good self-isolation effect,but the problem of the high voltage interconnection(HVI) line will become serious.The two step field plates including the source field plate and gate field plate can be adopted to shield the HVI adverse effect on the device.Based on this model,the TSL LVD SOI n-channel lateral double-diffused MOSFET(nLDMOS) with MSFP is realized.The experimental breakdown voltage(BV) and specific on-resistance(R on,sp) of the TSL LVD SOI device are 694 V and 21.3 ·mm 2 with a drift region length of 60 μm,buried oxide layer of 3 μm,and silicon layer of 0.15 μm,respectively.     

Flicker noise of hot electrons in silicon at T = 78 K

From flicker-noise and current-voltage measurements performed on an n⁺nn⁺ silicon planar device at T = 78 K we calculated Hooge's parameter α as a function of the electric field strength, E₀. We found that α(E₀) = α(0)/[1 + (E₀/E_c)²]. E_c is a critical field where the drift velocity equals the sound velocity, indicating the connection of the observed effect with acoustical phonon scattering.     

离子注入形成SOI结构的界面及埋层的俄歇能谱研究

本文中研究了O⁺(200keV,1.8×10¹⁸/cm²)和N⁺(190keV,1.8×10¹⁸/cm²)注入Si形成SOI(Silicon on Insulator)结构的界面及埋层的化学组成。俄歇能谱的测量和研究结果表明:注O⁺的SOI结构在经1300℃,5h退火后,其表层Si和氧化硅埋层的界面存在一个不饱和氧化硅状态,氧化硅埋层是由SiO₂相和这不饱和氧化硅态组成,而且氧化硅埋层和体硅界面不同于表层Si和氧化硅埋层界面;注N⁺的SOI结构在经1200℃,2h退火后,其氮化硅埋层中存在一个富N的疏松夹层,表层Si和氮化硅埋层界面与氮化硅埋层和体硅界面性质亦不同。这些结果与红外吸收和透射电子显微镜及离子背散射谱的分析结果相一致。还对两种SOI结构界面与埋层的不同特征的原因进行了分析讨论。 关键词：     

A novel partial SOI LDMOSFET with a trench and buried P layer for breakdown voltage improvement

In this paper for the first time, a partial silicon-on-insulator (PSOI) lateral double-diffused metal-oxide-semiconductor-field-effect-transistor (LDMOSFET) is proposed with a novel trench which improves breakdown voltage. The introduced trench in the partial buried oxide enhances peak of the electric field and is positioned in the drain side of the drift region to maximize breakdown voltage. We demonstrate that the electric field is modified by producing two additional electric field peaks, which decrease the common peaks near the drain and gate junctions in the trench-partial-silicon-on-insulator (T-PSOI) structure. Hence, a more uniform electric field is obtained. Two dimensional (2D) simulations show that the breakdown voltage of T-PSOI is nearly 64% higher in comparison with partial silicon on insulator (PSOI) structure and alleviate self heating effect approximately 9% and 15% in comparison with its conventional PSOI (C-PSOI) and conventional SOI (C-SOI) counterparts respectively. In addition the current of the T-PSOI, C-PSOI, conventional SOI (C-SOI), and fully depleted conventional SOI (FC-SOI) structures are 90, 82, 74, and 44 μA, respectively for a drain–source voltage V_DS = 30 V and gate–source voltage V_GS = 10 V.     

Enhanced field emission characteristics of thin-Au-coated nano-sheet carbon films

This paper reports that the nano-sheet carbon films (NSCFs) were fabricated on Si wafer chips with hydrogen--methane gas mixture by means of quartz-tube-type microwave plasma chemical vapour deposition (MWPCVD). In order to further improve the field emission (FE) characteristics, a 5-nm Au film was prepared on the samples by using electron beam evaporation. The FE properties were obviously improved due to depositing Au thin film on NSCFs. The FE current density at a macroscopic electric field, E, of 9~V/μ m was increased from 12.4~mA/cm² to 27.2~mA/cm² and the threshold field was decreased from 2.6~V/μ m to 2.0~V/μ m for Au-coated carbon films. A modified F-N model considering statistic effects of FE tip structures in the low E region and a space-charge-limited-current effect in the high E region were applied successfully to explain the FE data of the Au-coated NSCF.     

Ultra-low on-resistance high voltage (>600 V) SOI MOSFET with a reduced cell pitch

A low specific on-resistance (R S,on) silicon-on-insulator (SOI) trench MOSFET (metal-oxide-semiconductor-field-effect-transistor) with a reduced cell pitch is proposed.The lateral MOSFET features multiple trenches:two oxide trenches in the drift region and a trench gate extended to the buried oxide (BOX) (SOI MT MOSFET).Firstly,the oxide trenches increase the average electric field strength along the x direction due to lower permittivity of oxide compared with that of Si;secondly,the oxide trenches cause multiple-directional depletion,which improves the electric field distribution and enhances the reduced surface field (RESURF) effect in the SOI layer.Both of them result in a high breakdown voltage (BV).Thirdly,the oxide trenches cause the drift region to be folded in the vertical direction,leading to a shortened cell pitch and a reduced R S,on.Fourthly,the trench gate extended to the BOX further reduces R S,on,owing to the electron accumulation layer.The BV of the MT MOSFET increases from 309 V for a conventional SOI lateral double diffused metal-oxide semiconductor (LDMOS) to 632 V at the same half cell pitch of 21.5 μm,and R S,on decreases from 419 m · cm 2 to 36.6 m · cm 2.The proposed structure can also help to dramatically reduce the cell pitch at the same breakdown voltage.     

Averaged local field intensities in composite films

The photophysical properties of molecules adsorbed in composite films (e.g. surface island films) depend on the local electromagnetic field within the film. The ratio between the average field intensity 〈|E|²〉 in the film and the intensity |E_I|² associated with the incident field is a measure of the electromagnetic contribution to the surface influence on molecular photophysical phenomena. This ratio depends on the film composition and morphology, on the dielectric properties of the pure components making the film and on the frequency, direction and polarization of the incident radiation. Calculations of this ratio as a function of these parameters for several models of composite films are presented. Image interactions and retardation effects as well as radiative damping and finite size contributions to the dielectric response of the films are taken into account. In addition, an estimate of the field inhomogeneity within the film is obtained by calculating also the ratio 〈|E|²〉_shell/|E_I|² associated with the field in thin shells surrounding the dielectric particles which constitute the film.     

The electrical characteristics of a 4H-silicon carbide metal-insulator-semiconductor structure with Al2O3 as the gate dielectric

A 4H-silicon carbide metal-insulator-semiconductor structure with ultra-thin Al₂O₃ as the gate dielectric, deposited by atomic layer deposition on the epitaxial layer of a 4H-SiC (0001) 8⁰N-/N+ substrate, has been fabricated. The experimental results indicate that the prepared ultra-thin Al₂O₃ gate dielectric exhibits good physical and electrical characteristics, including a high breakdown electrical field of 25 MV/cm, excellent interface properties (1×10¹⁴ cm^-2) and low gate-leakage current (I_G = 1 × 10^-3 A/cm^-2@E_ox = 8 MV/cm). Analysis of the current conduction mechanism on the deposited Al₂O₃ gate dielectric was also systematically performed. The confirmed conduction mechanisms consisted of Fowler-Nordheim (FN) tunneling, the Frenkel-Poole mechanism, direct tunneling and Schottky emission, and the dominant current conduction mechanism depends on the applied electrical field. When the gate leakage current mechanism is dominated by FN tunneling, the barrier height of SiC/Al₂O₃ is 1.4 eV, which can meet the requirements of silicon carbide metal-insulator-semiconductor transistor devices.     

A new analytical model of high voltage silicon on insulator （SOI） thin film devices

A new analytical model of high voltage silicon on insulator (SOI) thin film devices is proposed, and a formula of silicon critical electric field is derived as a function of silicon film thickness by solving a 2D Poisson equation from an effective ionization rate, with a threshold energy taken into account for electron multiplying. Unlike a conventional silicon critical electric field that is constant and independent of silicon film thickness, the proposed silicon critical electric field increases sharply with silicon film thickness decreasing especially in the case of thin films, and can come to 141V/μm at a film thickness of 0.1μm which is much larger than the normal value of about 30V/μm. From the proposed formula of silicon critical electric field, the expressions of dielectric layer electric field and vertical breakdown voltage (V_B,V) are obtained. Based on the model, an ultra thin film can be used to enhance dielectric layer electric field and so increase vertical breakdown voltage for SOI devices because of its high silicon critical electric field, and with a dielectric layer thickness of 2μm the vertical breakdown voltages reach 852 and 300V for the silicon film thicknesses of 0.1 and 5μm, respectively. In addition, a relation between dielectric layer thickness and silicon film thickness is obtained, indicating a minimum vertical breakdown voltage that should be avoided when an SOI device is designed. 2D simulated results and some experimental results are in good agreement with analytical results.     

Study of a double epi-layers SiC junction barrier Schottky rectifiers embedded P layer in the drift region

<正>This paper proposes a double epi-layers 4H—SiC junction barrier Schottky rectifier(JBSR) with embedded P layer (EPL) in the drift region.The structure is characterized by the P-type layer formed in the n-type drift layer by epitaxial overgrowth process.The electric field and potential distribution are changed due to the buried P-layer,resulting in a high breakdown voltage(BV) and low specific on-resistance(R_(on,sp)).The influences of device parameters,such as the depth of the embedded P+ regions,the space between them and the doping concentration of the drift region,etc.,on BV and R_(on,sp) are investigated by simulations,which provides a particularly useful guideline for the optimal design of the device.The results indicate that BV is increased by 48.5%and Baliga's figure of merit(BFOM) is increased by 67.9%compared to a conventional 4H-SiC JBSR.     

The Numerical Simulation of the Nanosecond Switching of a <Emphasis Type="Italic">p</Emphasis>-SOS Diode

Abrupt high-density reverse current interruption has been numerically simulated for switching from forward to reverse bias in a silicon p⁺P₀n⁺ structure (p-SOS diode). It has been shown that the current interruption in this structure occurs as a result of the formation of two dynamic domains of a strong electric field in regions in which the free carrier concentration substantially exceeds the concentration of the doping impurity. The first domain is formed in the n⁺ region at the n⁺P⁰ junction, while the second domain is formed in the P⁰ region at the interface with the p⁺ layer. The second domain expands much faster, and this domain mainly determines the current interruption rate. Good agreement is achieved between the simulation results and the experimental data when the actual electric circuit determining the electron–hole plasma pumping in and out is accurately taken into account.     

A novel high-voltage light punch-through carrier stored trench bipolar transistor with buried p-layer

A novel high-voltage light punch-through(LPT) carrier stored trench bipolar transistor(CSTBT) with buried p-layer(BP) is proposed in this paper.Since the negative charges in the BP layer modulate the bulk electric field distribution,the electric field peaks both at the junction of the p base/n-type carrier stored(N-CS) layer and the corners of the trench gates are reduced,and new electric field peaks appear at the junction of the BP layer/N drift region.As a result,the overall electric field in the N drift region is enhanced and the proposed structure improves the breakdown voltage(BV) significantly compared with the LPT CSTBT.Furthermore,the proposed structure breaks the limitation of the doping concentration of the N-CS layer(NN CS) to the BV,and hence a higher NN CS can be used for the proposed LPT BP-CSTBT structure and a lower on-state voltage drop(Vce(sat)) can be obtained with almost constant BV.The results show that with a BP layer doping concentration of NBP = 7 × 1015 cm-3,a thickness of LBP = 2.5 μm,and a width of WBP = 5 μm,the BV of the proposed LPT BP-CSTBT increases from 1859 V to 1862 V,with NN CS increasing from 5 × 1015 cm-3 to 2.5 × 1016 cm-3.However,with the same N-drift region thickness of 150 μm and NN CS,the BV of the CSTBT decreases from 1598 V to 247 V.Meanwhile,the Vce(sat) of the proposed LPT BP-CSTBT structure decreases from 1.78 V to 1.45 V with NN CS increasing from 5 × 1015 cm-3 to 2.5 × 1016 cm-3.     

直流偏置电场下BaTiO３基陶瓷介电常数非线性机理的研究

采用传统固相法制备了Ba_0.6Sr_0.4TiO_３(BST)和BaZr< sub>xTi_１-xO_３(x=0.25，0.3，0.35，0.4)（ＢＺＴ）陶瓷 ，并对其在直流偏置电场下的介电常数非线性行为进行了系统、详细的研究.结果表明，基 于Devonshire的宏观相变理论(phenomenological theory)提出的公式ε_r(app) ε_r(0)=1［1+αε^{３_{r(0)E２ ］1/3和ε(E)=ε1－ε2E2+ε3E4，均可定量地解释BST体系顺电相的介电常数非线性行为，其中εr (app)表示材料在电场下的介电常数，εr(0)表示不加电场即静态下材料 的介电常数，α是非谐性因子，E表示电场强度，ε(E)表示材料在电场下的介电常数，ε１，ε２，ε３分别表示线性、非线性和高阶介电常数. 而对于处于铁电相和居里温度附近的BST体系，则需要考虑铁电畴对介电常数非线性的贡献 ，这种贡献随着外加直流偏置电场强度的增大逐步减小.对于弛豫铁电体BZT体系，即使处于 顺电相，也必须考虑由极性微区的冻结与合并引起的介电常数的下降，极性微区对介电常数 非线性的贡献随着电场强度和温度的上升而有所下降. 关键词： BST x}Ti_１-xO_３')" href="#">BaZr_xTi_１-xO_３ 可调性 介电 常数非线性 直流偏置电场}