阶梯氧化层新型折叠硅横向双扩散功率器件

为了设计功率集成电路所需的低功耗横向功率器件, 提出了一种具有阶梯氧化层折叠硅横向双扩散金属-氧化物-半导体(step oxide folding LDMOS, SOFLDMOS)新结构. 这种结构将阶梯氧化层覆盖在具有周期分布的折叠硅表面, 利用阶梯氧化层的电场调制效应, 通过在表面电场分布中引入新的电场峰而使表面电场分布均匀, 提高了器件的耐压范围, 解决了文献提出的折叠积累型横向双扩散金属-氧化物-半导体器件击穿电压受限的问题. 通过三维仿真软件ISE分析获得, SOFLDMOS 结构打破了硅的极限关系, 充分利用了电场调制效应、多数载流子积累和硅表面导电区倍增效应, 漏极饱和电流比一般LDMOS 提高3.4倍左右, 可以在62 V左右的反向击穿电压条件下, 获得0.74 mΩ·cm²超低的比导通电阻, 远低于传统LDMOS相同击穿电压下2.0 mΩ·cm²比导通电阻, 为实现低压功率集成电路对低功耗横向功率器件的要求提供了一种可选的方案.     

具有P型覆盖层新型超级结横向双扩散功率器件

为了设计功率集成电路所需要的低功耗横向双扩散金属氧化物半导体器件(lateral double-diffused MOSFET), 在已有的N型缓冲层超级结LDMOS(N-buffered-SJ-LDMOS)结构基础上, 提出了一种具有P型覆盖层新型超级结LDMOS结构(P-covered-SJ-LDMOS). 这种结构不但能够消除传统的N沟道SJ-LDMOS由于P型衬底产生的衬底辅助耗尽问题, 使得超级结层的N区和P区的电荷完全补偿, 而且还能利用覆盖层的电荷补偿作用, 提高N型缓冲层浓度, 从而降低了器件的比导通电阻. 利用三维仿真软件ISE分析表明, 在漂移区长度均为10 μm的情况下, P-covered-SJ-LDMOS的比导通电阻较一般SJ-LDMOS结构降低了59%左右, 较文献提出的N型缓冲层 SJ-LDMOS(N-buffered-SJ-LDMOS)结构降低了43%左右.     

具有半绝缘多晶硅完全三维超结横向功率器件

为了突破传统LDMOS (lateral double-diffused MOSFET)器件击穿电压与比导通电阻的硅极限的2.5 次方关系, 降低LDMOS器件的功率损耗, 提高功率集成电路的功率驱动能力, 提出了一种具有半绝缘多晶硅SIPOS (semi-insulating poly silicon)覆盖的完全3 D-RESURF (three-dimensional reduced surface field)新型Super Junction-LDMOS结构(SIPOS SJ-LDMOS). 这种结构利用SIPOS的电场调制作用使SJ-LDMOS的表面电场分布均匀, 将器件单位长度的耐压量提高到19.4 V/μupm; 覆盖于漂移区表面的SIPOS使SJ-LDMOS沿三维方向均受到电场调制, 实现了LDMOS的完全3 D-RESURF效应, 使更高浓度的漂移区完全耗尽而达到高的击穿电压; 当器件开态工作时, 覆盖于薄场氧化层表面的SIPOS的电场作用使SJ-LDMOS的漂移区表面形成多数载流子积累, 器件比导通电阻降低. 利用器件仿真软件ISE分析获得, 当SIPOS SJ-LDMOS的击穿电压为388 V时, 比导通电阻为20.87 mΩ·cm², 相同结构参数条件下, N-buffer SJ-LDMOS的击穿电压为287 V, 比导通电阻为31.14 mΩ·cm²; 一般SJ-LDMOS 的击穿电压仅为180 V, 比导通电阻为71.82 mΩ·cm².     

具有纵向辅助耗尽衬底层的新型横向双扩散金属氧化物半导体场效应晶体管

为了优化横向双扩散金属氧化物半导体场效应晶体管(lateral double-diffused MOSFET,LDMOS)的击穿特性及器件性能,在传统LDMOS结构的基础上,提出了一种具有纵向辅助耗尽衬底层(assisted depletesubstrate layer,ADSL)的新型LDMOS.新加入的ADSL层使得漏端下方的纵向耗尽区大幅向衬底扩展,从而利用电场调制效应在ADSL层底部引入新的电场峰,使纵向电场得到优化,同时横向表面电场也因为电场调制效应而得到了优化.通过ISE仿真表明,当传统LDMOS与ADSL LDMOS的漂移区长度都是70μm时,击穿电压由462 V增大到897 V,提高了94%左右,并且优值也从0.55 MW/cm~2提升到1.24 MW/cm~2,提升了125%.因此,新结构ADSL LDMOS的器件性能较传统LDMOS有了极大的提升.进一步对ADSL层进行分区掺杂优化,在新结构的基础上,击穿电压在双分区时上升到938 V,三分区时为947 V.     

衬底浮空的新型绝缘体上硅基横向功率器件分析

针对有机半导体领域的发展要求,报道了一种能够应用于有机半导体领域衬底浮空的新型SOI LDMOS(silicon on insulator lateral double-diffused metal oxide semiconductor)功率器件,不同于传统无机半导体中SOI LDMOS功率器件,该新型器件可以与绝缘...     

具有部分超结的新型SiC SBD特性分析

提出了一种具有部分超结（super junction, SJ）结构的新型SiC肖特基二极管,命名为SiC Semi-SJ-SBD结构,通过将常规SBD耐压区分为常规耐压区和超结耐压区来减小导通电阻,改善正向特性.利用二维器件模拟软件MEDICI仿真分析,研究了不同超结深度和厚度时击穿电压(V_B)和比导通电阻(R_on-sp),与常规结构的SBD比较得出,半超结结构可以明显改善SiC肖特基二极管特性,并得到优化的设计方案,选择超结宽度2< 关键词： SiC肖特基二极管 super junction 导通电阻 击穿电压     

高k介质电导增强SOI LDMOS机理与优化设计

本文提出一种高k介质电导增强SOI LDMOS新结构（HK CE SOI LDMOS）,并研究其机理. HK CE SOI LDMOS的特征是在漂移区两侧引入高k介质,反向阻断时,高k介质对漂移区进行自适应辅助耗尽,实现漂移区三维RESURF效应并调制电场,因而提高器件耐压和漂移区浓度并降低导通电阻. 借助三维仿真研究耐压、比导通电阻与器件结构参数之间的关系. 结果表明,HK CE SOI LDMOS与常规超结SOI LDMOS相比,耐压提高16%–18%,同时比导通电阻降低13%–20%,且缓解了由衬底辅助耗尽效应带来的电荷非平衡问题. 关键词： k介质')" href="#">高k介质 绝缘体上硅 (SOI) 击穿电压 比导通电阻     

具有N型缓冲层REBULF Super Junction LDMOS

针对功率集成电路对低损耗LDMOS (lateral double-diffused MOSFET)类器件的要求,在N型缓冲层super junction LDMOS (buffered SJ-LDMOS)结构基础上, 提出了一种具有N型缓冲层的REBULF (reduced BULk field) super junction LDMOS结构. 这种结构不但消除了N沟道SJ-LDMOS由于P型衬底带来的衬底辅助耗尽效应问题, 使super junction的N区和P区电荷完全补偿, 而且同时利用REBULF的部分N型缓冲层电场调制效应, 在表面电场分布中引入新的电场峰而使横向表面电场分布均匀, 提高了器件的击穿电压. 通过优化部分N型埋层的位置和参数, 利用仿真软件ISE分析表明, 新型REBULF SJ-LDMOS 的击穿电压较一般LDMOS提高了49%左右, 较文献提出的buffered SJ-LDMOS结构提高了30%左右. 关键词： lateral double-diffused MOSFET super junction 击穿电压 表面电场     

High-voltage super-junction lateral double-diffused metal-oxide semiconductor with a partial lightly doped pillar

A novel super-junction lateral double-diffused metal-oxide semiconductor(SJ-LDMOS) with a partial lightly doped P pillar(PD) is proposed.Firstly,the reduction in the partial P pillar charges ensures the charge balance and suppresses the substrate-assisted depletion effect.Secondly,the new electric field peak produced by the P/P-junction modulates the surface electric field distribution.Both of these result in a high breakdown voltage(BV).In addition,due to the same conduction paths,the specific on-resistance(R on,sp) of the PD SJ-LDMOS is approximately identical to the conventional SJ-LDMOS.Simulation results indicate that the average value of the surface lateral electric field of the PD SJ-LDMOS reaches 20V/μm at a 15μm drift length,resulting in a BV of 300V.     

Low on-resistance high-voltage lateral double-diffused metal oxide semiconductor with a buried improved super-junction layer

A novel low specific on-resistance （Ron,sp） lateral double-diffused metal oxide semiconductor （LDMOS） with a buried improved super-junction （BISJ） layer is proposed. A super-junction layer is buried in the drift region and the P pillar is split into two parts with different doping concentrations. Firstly, the buried super-junction layer causes the multiple-direction assisted depletion effect. The drift region doping concentration of the BISJ LDMOS is therefore much higher than that of the conventional LDMOS. Secondly, the buried super-junction layer provides a bulk low on-resistance path. Both of them reduce Ron,sp greatly. Thirdly, the electric field modulation effect of the new electric field peak introduced by the step doped P pillar improves the breakdown voltage （BV）. The BISJ LDMOS exhibits a BV of 300 V and Ron,sp of 8.08 mΩ·cm2 which increases BV by 35% and reduces Ron,sp by 60% compared with those of a conventional LDMOS with a drift length of 15 μm, respectively.     

A novel LDMOS with a junction field plate and a partial N-buried layer

A novel lateral double-diffused metal–oxide semiconductor (LDMOS) with a high breakdown voltage (BV) and low specific on-resistance (R_on.sp) is proposed and investigated by simulation. It features a junction field plate (JFP) over the drift region and a partial N-buried layer (PNB) in the P-substrate. The JFP not only smoothes the surface electric field (E-field), but also brings in charge compensation between the JFP and the N-drift region, which increases the doping concentration of the N-drift region. The PNB reshapes the equipotential contours, and thus reduces the E-field peak on the drain side and increases that on the source side. Moreover, the PNB extends the depletion width in the substrate by introducing an additional vertical diode, resulting in a significant improvement on the vertical BV. Compared with the conventional LDMOS with the same dimensional parameters, the novel LDMOS has an increase in BV value by 67.4%, and a reduction in R_on.sp by 45.7% simultaneously.     

A new analytical model for the surface electric field distribution and breakdown voltage of the SOI trench LDMOS

A new analytical model for the surface electric field distribution and breakdown voltage of the silicon on insulator (SOI) trench lateral double-diffused metal-oxide-semiconductor (LDMOS) is presented. Based on the two-dimensional Laplace solution and Poisson solution, the model considers the influence of structure parameters such as the doping concentration of the drift region, and the depth and width of the trench on the surface electric field. Further, a simple analytical expression of the breakdown voltage is obtained, which offers an effective way to gain an optimal high voltage. All the analytical results are in good agreement with the simulation results.     

High-voltage SOI lateral MOSFET with a dual vertical field plate

A new silicon-on-insulator(SOI)power lateral MOSFET with a dual vertical field plate(VFP)in the oxide trench is proposed.The dual VFP modulates the distribution of the electric field in the drift region,which enhances the internal field of the drift region and increases the drift doping concentration of the drift region,resulting in remarkable improvements in breakdown voltage(BV)and specific on-resistance(Ron,sp).The mechanism of the VFP is analyzed and the characteristics of BV and Ron,spare discussed.It is shown that the BV of the proposed device increases from 389 V of the conventional device to 589 V,and the Ron,sp decreases from 366 m·cm2to 110 m·cm2.