SOI部分耗尽SiGe HBT集电结空间电荷区模型

SOI上的薄膜异质SiGe晶体管通过采用"折叠"集电极,已成功实现SOI上CMOS与HBT的兼容.本文结合SOI薄膜上的纵向SiGe HBT结构模型,提出了包含纵向、横向欧姆电阻和耗尽电容的"部分耗尽 (partially depleted) 晶体管"集电区简化电路模型.基于器件物理及实际考虑,系统建立了外延集电层电场、电势、耗尽宽度模型,并根据该模型对不同器件结构参数进行分析.结果表明,空间电荷区表现为本征集电结耗尽与MOS电容耗尽,空间电荷区宽度随集电结掺杂浓度减小而增大,随集电结反偏电压提高而增大, 关键词： SOI SiGe HBT 集电区 空间电荷区模型     

SiGe HBT势垒电容模型

在考虑SiGe HBT的势垒电容时，通常的耗尽层近似不再适用，应考虑可动载流子的影响.在分析研究SiGe HBT载流子输运的基础上，建立了考虑发射结势垒区内载流子分布的发射结势垒电容模型和不同电流密度下包括基区扩展效应的集电结势垒电容模型.将以上势垒电容 模型应用于SiGe HBT频率特性模拟，模拟结果与实验结果符合得很好. 关键词： SiGe HBT 势垒电容 微分电容     

SOI SiGe HBT电学性能研究

研究了SOI衬底上SiGe npn异质结晶体管的设计优化.给出了器件基本直流交流特性曲线,分析了与常规SiGeHBT的不同.由于SOI衬底的引入使SOI SiGe HBT成为四端器件,重点研究了衬底偏压对Gummel曲线、输出特性曲线以及雪崩电流的影响.最后仿真实现材料物理参数和几何物理参数对频率特性的改变.结果表明SOI SiGeHBT与常规器件相比具有更大的设计自由度.SOI SiGe HBT的系统分析为毫米波SOI SiGe BiCMOS电路的设计提供了有价值的参考.     

SiGe HBT集电结耗尽层渡越时间模型

集电结耗尽层的渡越时间是影响晶体管交流放大系数和频率特性的重要参数。本文分三种情况求解了SiGe HBT集电结耗尽层宽度。建立了不同集电极电流密度下的集电结耗尽层渡越时间模型，该模型考虑了基区扩展效应。利用MATLAB对该模型进行了模拟，定量地研究了集电结反偏电压、集电区掺杂磷或砷的浓度、集电区宽度对集电结耗尽层渡越时间的影响。模拟结果表明：随着集电结反偏电压、集电区掺杂浓度以及集电区宽度的增大，集电结耗尽层渡越时间增大；集电结耗尽层渡越时间对薄基区的SiGe HBT频率特性影响显著，不能忽略。     

SOI SiGe HBT结构设计及频率特性研究

将SOI技术优势引入SiGe HBT,可满足当前BiCMOS高速低功耗的应用需求.SOI SiGe HBT作为BiCMOS工艺的核心器件,其频率特性决定了电路所能达到的工作速度.为此,本文针对所提出的SOI SiGe HBT器件结构,重点研究了该器件的频率特性,并通过所建立的集电区电容模型予以分析.规律和结果为:1)SOI SiGe HBT特征频率随集电区掺杂浓度的升高而增加;2)SOI SiGe HBT特征频率与集电极电流IC之间的变化规律与传统SiGe HBT的相一致;3)正常工作状态,SOI SiGe HBT(集电区3×1017cm-3掺杂)最高振荡频率fmax大于140 GHz,且特征频率fT大于60 GHz.与传统SiGe HBT相比,特征频率最大值提高了18.84%.以上规律及结论可为SOI SiGe HBT及BiCMOS的研究设计提供重要依据.     

SiGe HBT大信号等效电路模型

基于SiGe HBT(异质结双极晶体管)的物理模型，建立了描述SiGe HBT的大信号等效电路模型.该等效电路模型考虑了准饱和效应和自热效应等，模型分为本征和非本征两部分，物理意义清晰，拓扑结构相对简单.该模型嵌入了PSPICE软件的DEVEO(器件方程开发包)中.在PSPICE软件资源的支持下，利用该模型对SiGe HBT器件进行了交直流特性模拟分析，模拟结果与理论分析结果相一致，并且与文献报道的结果符合较好. 关键词： SiGe HBT 等效电路模型 PSPICE     

含有本征SiGe层的SiGe异质结双极晶体管集电结耗尽层宽度模型

本文分别建立了含有本征SiGe层的SiGe HBT(异质结双极晶体管)集电结耗尽层各区域的电势、电场分布模型,并在此基础上,建立了集电结耗尽层宽度和延迟时间模型,对该模型进行了模拟仿真,定量地分析了SiGe HBT物理、电学参数对集电结耗尽层宽度和延迟时间的影响,随着基区掺杂浓度和集电结反偏电压的提高,集电结耗尽层延迟时间也随之增大,而随着集电区掺杂浓度的提高和基区Ge组分增加,集电结耗尽层延迟时间随之减小. 关键词： SiGe HBT 集电结耗尽层 延迟时间     

应变SiGe SOI量子阱沟道PMOSFET阈值电压模型研究

在绝缘层附着硅(SOI)结构的Si膜上生长SiGe合金制作具有SiGe量子阱沟道的SOI p型金属氧化物半导体场效应晶体管(PMOSFET)，该器件不仅具有SOI结构的优点，而且因量子阱中载流子迁移率高，所以进一步提高了器件的性能.在分析常规的Si SOI MOSFET基础上，建立了应变SiGe SOI 量子阱沟道PMOSFET的阈值电压模型和电流-电压(I-V)特性模型，利用Matlab对该结构器件的I-V特性、跨导及漏导特性进行了模拟分析，且与常规结构的器件作了对比.模拟结果表明，应变SiGe SOI量子阱沟道PMOSFET的性能均比常规结构的器件有大幅度提高. 关键词： 应变SiGe SOI MOSFET 阈值电压 模型     

部分耗尽SOI晶体管电离辐射损伤的物理模型

从氧化层俘获空穴和质子诱导界面态形成的物理机制出发,建立部分耗尽SOI器件总剂量辐射诱导的氧化层陷阱电荷和界面态物理模型,模型可以很好地描述辐射诱导氧化层陷阱电荷和界面态与辐射剂量的关系,并从实验上对上述模型结果给予验证.结果表明,在实验采用的辐射剂量范围内,辐射诱导产生的氧化物陷阱电荷与辐射剂量满足负指数关系.模型中如果考虑空穴的退火效应,可以更好地反映高剂量辐照下的效应;辐射诱导产生的界面态与辐射剂量成正比例关系.     

应变SiGe p 型金属氧化物半导体场效应管栅电容特性研究

由于台阶的出现, 应变SiGe p型金属氧化物半导体场效应管 (pMOSFET) 的栅电容特性与体Si器件的相比呈现出很大的不同, 且受沟道掺杂的影响严重. 本文在研究应变SiGe pMOSFET器件的工作机理及其栅电容C-V 特性中台阶形成机理的基础上, 通过求解器件不同工作状态下的电荷分布, 建立了应变SiGe pMOSFET栅电容模型, 探讨了沟道掺杂浓度对台阶的影响. 与实验数据的对比结果表明, 所建立模型能准确反映应变SiGe pMOSFET器件的栅电容特性, 验证了模型的正确性. 该理论为Si基应变金属氧化物半导体(MOS)器件的设计制造提供了重要的指导作用, 并已成功应用于Si基应变器件模型参数提取软件中, 为Si基应变MOS的仿真奠定了理论基础. 关键词： 应变SiGe pMOSFET 栅电容特性 台阶效应 沟道掺杂     

A technique for simultaneously improving the product of cutoff frequency–breakdown voltage and thermal stability of SOI SiGe HBT

The product of the cutoff frequency and breakdown voltage( fT×BVCEO) is an important figure of merit(FOM) to characterize overall performance of heterojunction bipolar transistor(HBT). In this paper, an approach to introducing a thin N+-buried layer into N collector region in silicon-on-insulator(SOI) Si Ge HBT to simultaneously improve the FOM of fT×BVCEOand thermal stability is presented by using two-dimensional(2D) numerical simulation through SILVACO device simulator. Firstly, in order to show some disadvantages of the introduction of SOI structure, the effects of SOI insulation layer thickness(TBOX) on fT, BVCEO, and the FOM of fT×BVCEOare presented. The introduction of SOI structure remarkably reduces the electron concentration in collector region near SOI substrate insulation layer, obviously reduces fT, slightly increases BVCEOto some extent, but ultimately degrades the FOM of fT×BVCEO. Although the fT,BVCEO, and the FOM of fT×BVCEOcan be improved by increasing SOI insulator Si O_2 layer thickness TBOXin SOI structure, the device temperature and collector current are increased due to lower thermal conductivity of Si O_2 layer, as a result, the self-heating effect of the device is enhanced, and the thermal stability of the device is degraded. Secondly, in order to alleviate the foregoing problem of low electron concentration in collector region near SOI insulation layer and the thermal stability resulting from thick TBOX, a thin N+-buried layer is introduced into collector region to not only improve the FOM of fT×BVCEO, but also weaken the self-heating effect of the device, thus improving the thermal stability of the device. Furthermore, the effect of the location of the thin N+-buried layer in collector region is investigated in detail. The result show that the FOM of fT×BVCEOis improved and the device temperature decreases as the N+-buried layer shifts toward SOI substrate insulation layer. The approach to introducing a thin N+-buried layer into collector region provides an effective method to improve SOI Si Ge HBT overall performance.     

Analytical base–collector depletion capacitance in vertical SiGe heterojunction bipolar transistors fabricated on CMOS-compatible silicon on insulator

The base--collector depletion capacitance for vertical SiGe npn heterojunction bipolar transistors (HBTs) on silicon on insulator (SOI) is split into vertical and lateral parts. This paper proposes a novel analytical depletion capacitance model of this structure for the first time. A large discrepancy is predicted when the present model is compared with the conventional depletion model, and it is shown that the capacitance decreases with the increase of the reverse collector--base bias--and shows a kink as the reverse collector--base bias reaches the effective vertical punch-through voltage while the voltage differs with the collector doping concentrations, which is consistent with measurement results. The model can be employed for a fast evaluation of the depletion capacitance of an SOI SiGe HBT and has useful applications on the design and simulation of high performance SiGe circuits and devices.     

Oxidation process of SiGe on SOI substrates

The oxidation of SiGe film epitaxial grown on top of SOI wafers has been studied. These SiGe/SOI samples were oxidized at 700, 900, 1100 °C. Germanium atoms were rejected from SiGe film to SOI layer. A new Si_1−xGe_x (x is minimal) layer formed at SiGe/Si interface. As the germanium atoms diffused, the new Si_1−xGe_x (x is minimal) layer moved to Si/SiO₂ interface. Propagation of threading dislocation in SiGe film to SOI substrate was hindered by the new SiGe/Si interface. Strain in SOI substrate transferred from SiGe film was released through dislocation nucleation and propagation inner. The relaxation of SiGe film could be described as: strain relaxed through strain equalization and transfer process between SiGe film and SOI substrates. Raman spectroscopy was used to characterize the strain of SiGe film. Microstructure of SiGe/SOI was observed by transmission electron microscope (TEM).     

Extraction of temperature dependences of small-signal model parameters in SiGe HBT HICUM model

In this work, temperature dependences of small-signal model parameters in the SiGe HBT HICUM model are presented. Electrical elements in the small-signal equivalent circuit are first extracted at each temperature, then the temperature dependences are determined by the series of extracted temperature coefficients, based on the established temperature formulas for corresponding model parameters. The proposed method is validated by a 1 × 0.2 × 16 μm~2 SiGe HBT over a wide temperature range(from 218 K to 473 K), and good matching is obtained between the extracted and modeled results. Therefore, we believe that the proposed extraction flow of model parameter temperature dependence is reliable for characterizing the transistor performance and guiding the circuit design over a wide temperature range.     

Comparative study of low frequency noise and hot-carrier reliability in SiGe PD SOI pMOSFETs

The stress effect of SiGe pMOSFETs has been investigated to understand the electrical properties of devices fabricated on the Si bulk and PD SOI substrates. A comparison of the drain saturation current (I_D.sat) and maximum transconductance (g_m,max) in both the SiGe bulk and the SiGe PD SOI devices clearly shows that the SiGe PD SOI is more immune from hot-carriers than the SiGe bulk. The stress-induced leakage current (SILC) is hardly detectable in ultra-thin oxide, because the increasing contribution of direct tunneling is comparable to the trap-assisted component. The SiGe PD SOI revealed degraded properties being mainly associated with the detrimental silicon-oxide interface states of the SOI structure.