Investigation of an AlInAs/GaInAs superlattice-emitter resonant tunneling bipolar transistor (SE-RTBT)

A new bipolar transistor with a 20-period i-AlInAs/n⁺-InGaAs superlattice, prepared by metal organic chemical vapour deposition, has been fabricated and demonstrated. This superlattice is used as a confinement barrier for holes and a resonant tunneling (RT) route for electrons. Due to the RT effect within the 20-period superlattice near emitter–base p–n junction region, the N-shaped negative-differential-resistance (NDR) phenomena are observed under normal operation. A transistor action with a common-emitter current gain of 13 and a small offset voltage (90 mV) is achieved at room temperature.     

伽玛辐照对SiGe异质结双极型晶体管的集电极电流和厄尔利电压的影响

 研究了伽玛辐照效应对SiGe异质结双极型晶体管的集电极电流和厄尔利电压的影响。经过10⁴ Gy的伽玛总剂量辐照后,集电极电流和厄尔利电压均增加。另外,辐照后发射结和极电结的开启电压和击穿电压也均有一定程度的减小。以上这些变化均是由于辐照产生的缺陷引起发射区和集电区有效掺杂浓度减小所致。     

伽玛辐照对SiGe异质结双极型晶体管的集电极电流和厄尔利电压的影响

研究了伽玛辐照效应对SiGe异质结双极型晶体管的集电极电流和厄尔利电压的影响。经过104 Gy的伽玛总剂量辐照后,集电极电流和厄尔利电压均增加。另外,辐照后发射结和极电结的开启电压和击穿电压也均有一定程度的减小。以上这些变化均是由于辐照产生的缺陷引起发射区和集电区有效掺杂浓度减小所致。     

抗辐射双极n-p-n晶体管的研究

根据发射极周长与面积比(P/A)最小的原则,优化设计了双极n-p-n晶体管的尺寸参数,采用20 V双极型工艺设计制造了三种抗辐射加固的n-p-n晶体管.测试表明,在总剂量为1 kGy的辐照条件下,所制备的发射结加固型n-p-n晶体管和含有重掺杂基区环的n-p-n晶体管,辐照后的电流增益比常规结构的n-p-n晶体管高10%-15%;而两种加固措施都有的n-p-n晶体管,辐照后的电流增益比常规结构的n-p-n晶体管高15%-20%. 关键词： 双极n-p-n晶体管 辐射效应 电流增益 抗辐射     

A novel 4H-SiC lateral bipolar junction transistor structure with high voltage and high current gain

In this paper, a novel structure of a 4H-SiC lateral bipolar junction transistor (LBJT) with a base field plate and double RESURF in the drift region is presented. Collector-base junction depletion extension in the base region is restricted by the base field plate. Thin base as well as low base doping of the LBJT therefore can be achieved under the condition of avalanche breakdown. Simulation results show that thin base of 0.32 μm and base doping of 3×1017 cm-3 are obtained, and corresponding current gain is as high as 247 with avalanche breakdown voltage of 3309 V when the drift region length is 30 μm. Besides, an investigation of a 4H-SiC vertical BJT (VBJT) with comparable breakdown voltage (3357 V) shows that the minimum base width of 0.25 μm and base doping as high as 8×1017 cm-3 contribute to a maximum current gain of only 128.     

含有本征SiGe层的SiGe异质结双极晶体管集电结耗尽层宽度模型

本文分别建立了含有本征SiGe层的SiGe HBT(异质结双极晶体管)集电结耗尽层各区域的电势、电场分布模型,并在此基础上,建立了集电结耗尽层宽度和延迟时间模型,对该模型进行了模拟仿真,定量地分析了SiGe HBT物理、电学参数对集电结耗尽层宽度和延迟时间的影响,随着基区掺杂浓度和集电结反偏电压的提高,集电结耗尽层延迟时间也随之增大,而随着集电区掺杂浓度的提高和基区Ge组分增加,集电结耗尽层延迟时间随之减小. 关键词： SiGe HBT 集电结耗尽层 延迟时间     

A high voltage silicon-on-insulator lateral insulated gate bipolar transistor with a reduced cell-pitch

A high voltage( 600 V) integrable silicon-on-insulator(SOI) trench-type lateral insulated gate bipolar transistor(LIGBT) with a reduced cell-pitch is proposed.The LIGBT features multiple trenches(MTs):two oxide trenches in the drift region and a trench gate extended to the buried oxide(BOX).Firstly,the oxide trenches enhance electric field strength because of the lower permittivity of oxide than that of Si.Secondly,oxide trenches bring in multi-directional depletion,leading to a reshaped electric field distribution and an enhanced reduced-surface electric-field(RESURF) effect.Both increase the breakdown voltage(BV).Thirdly,oxide trenches fold the drift region around the oxide trenches,leading to a reduced cell-pitch.Finally,the oxide trenches enhance the conductivity modulation,resulting in a high electron/hole concentration in the drift region as well as a low forward voltage drop(Von).The oxide trenches cause a low anode-cathode capacitance,which increases the switching speed and reduces the turn-off energy loss(Eoff).The MT SOI LIGBT exhibits a BV of 603 V at a small cell-pitch of 24 μm,a Von of 1.03 V at 100 A/cm-2,a turn-off time of 250 ns and Eoff of 4.1×10?3 mJ.The trench gate extended to BOX synchronously acts as dielectric isolation between high voltage LIGBT and low voltage circuits,simplifying the fabrication processes.     

双极型晶体管损坏与强电磁脉冲注入位置的关系

利用时域有限差分法,对双极型晶体管(BJT)在强电磁脉冲作用下的瞬态响应进行了2维数值模拟,研究了电磁脉冲从不同极板注入时BJT的响应情况,根据温度分布的集中程度分析了发生烧毁的难易程度。模拟得出：发射极注入最容易导致烧毁,集电极注入次之,基极注入相对不易导致烧毁;发射极注入烧毁所消耗能量随着脉冲电压上升而下降,到30 V以后基本与电压的升高无关,集电极注入烧毁所消耗的能量则随着电压上升而上升,到100 V以后由于BE结上热点的出现而开始下降。     

Thermal analytic model of current gain for bipolar junction transistor-bipolar static induction transistor compound device

This paper proposes a thermal analytical model of current gain for bipolar junction transistor-bipolar static induction transistor (BJT-BSIT) compound device in the low current operation. It also proposes a best thermal compensating factor to the compound device that indicates the relationship between the thermal variation rate of current gain and device structure. This is important for the design of compound device to be optimized. Finally, the analytical model is found to be in good agreement with numerical simulation and experimental results. The test results demonstrate that thermal variation rate of current gain is below 10% in 25℃--85℃ and 20{\%} in -55℃--25℃.     

Early effect modeling of silicon-on-insulator SiGe heterojunction bipolar transistors

Silicon germanium(SiGe) heterojunction bipolar transistor(HBT) on thin silicon-on-insulator(SOI) has recently been demonstrated and integrated into the latest SOI BiCMOS technology.The Early effect of the SOI SiGe HBT is analysed considering vertical and horizontal collector depletion,which is different from that of a bulk counterpart.A new compact formula of the Early voltage is presented and validated by an ISE TCAD simulation.The Early voltage shows a kink with the increase of the reverse base-collector bias.Large differences are observed between SOI devices and their bulk counterparts.The presented Early effect model can be employed for a fast evaluation of the Early voltage and is useful to the design,the simulation and the fabrication of high performance SOI SiGe devices and circuits.     

双极型晶体管在强电磁脉冲作用下的瞬态响应

 利用时域有限差分法,对双极型晶体管在强电磁脉冲作用下的瞬态响应进行了2维数值模拟,分析了器件烧毁过程中电场、电流密度、温度等参数的分布及变化情况,分别观察了低电压和高电压脉冲作用下烧毁过程中热点的形成过程,并得到了器件烧毁所需时间以及能量与脉冲电压幅度之间的关系。在电压脉冲较低时,烧毁点位于通道中靠近集电极的位置,当脉冲电压达到一定幅度的时候,由于发射极与集电极之间发生雪崩击穿,基极和发射极之间电势会抬高,从而引起基极和发射极之间的击穿,形成新的热点,并在电压幅度约高于100 V的情况下会率先达到烧毁温度。随着脉冲电压幅度的增高,晶体管烧毁所需时间呈负指数减少,而所需能量在55~100 V之间接近于线性增长,直到电压幅度约高于100 V时才开始减少。     

双极型晶体管损坏与强电磁脉冲注入位置的关系

 利用时域有限差分法,对双极型晶体管(BJT)在强电磁脉冲作用下的瞬态响应进行了2维数值模拟,研究了电磁脉冲从不同极板注入时BJT的响应情况,根据温度分布的集中程度分析了发生烧毁的难易程度。模拟得出：发射极注入最容易导致烧毁,集电极注入次之,基极注入相对不易导致烧毁;发射极注入烧毁所消耗能量随着脉冲电压上升而下降,到30 V以后基本与电压的升高无关,集电极注入烧毁所消耗的能量则随着电压上升而上升,到100 V以后由于BE结上热点的出现而开始下降。     

A novel structure of a high current gain 4H-SiC BJT with a buried layer in base

In this paper, a new structure of a 4H-SiC bipolar junction transistor (BJT) with a buried layer (BL) in the base is presented. The current gain shows an approximately 100% increase compared with that of the conventional structure. This is attributed to the creation of a built-in electric field for the minority carriers to transport in the base which is explained based on 2D device simulations. The optimized design of the buried layer region is also considered by numeric simulations.     

An analytical threshold voltage model for dual-strained channel PMOSFET

Based on the analysis of vertical electric potential distribution across the dual-channel strained p-type Si/strained Si 1-x Ge x /relaxd Si 1-y Ge y (s-Si/s-SiGe/Si 1-y Ge y) metal-oxide-semiconductor field-effect transistor (PMOSFET),an-alytical expressions of the threshold voltages for buried channel and surface channel are presented.And the maximum allowed thickness of s-Si is given,which can ensure that the strong inversion appears earlier in the buried channel (compressive strained SiGe) than in the surface channel (tensile strained Si),because the hole mobility in the buried channel is higher than that in the surface channel.Thus they offer a good accuracy as compared with the results of device simulator ISE.With this model,the variations of threshold voltage and maximum allowed thickness of s-Si with design parameters can be predicted,such as Ge fraction,layer thickness,and doping concentration.This model can serve as a useful tool for p-channel s-Si/s-SiGe/Si 1-y Ge y metal-oxide-semiconductor field-effect transistor (MOSFET) designs.     

Effect of gate length on breakdown voltage in AlGaN/GaN high-electron-mobility transistor

The effects of gate length L_G on breakdown voltage VBRare investigated in AlGaN/GaN high-electron-mobility transistors(HEMTs) with L_G= 1 μm~20 μm. With the increase of L_G, VBRis first increased, and then saturated at LG= 3 μm. For the HEMT with L_G= 1 μm, breakdown voltage VBRis 117 V, and it can be enhanced to 148 V for the HEMT with L-_G= 3 μm. The gate length of 3 μm can alleviate the buffer-leakage-induced impact ionization compared with the gate length of 1 μm, and the suppression of the impact ionization is the reason for improving the breakdown voltage.A similar suppression of the impact ionization exists in the HEMTs with LG 3 μm. As a result, there is no obvious difference in breakdown voltage among the HEMTs with LG= 3 μm~20 μm, and their breakdown voltages are in a range of 140 V–156 V.     

Novel carbon nanotube field effect transistor with graded double halo channel

A novel carbon nanotube field effect transistor with symmetric graded double halo channel (GDH–CNTFET) is presented for suppressing band to band tunneling and improving the device performance. GDH structure includes two symmetric graded haloes which are broadened throughout the channel. The doping concentration of GDH channel is at maximum level at drain/source side and is reduced gradually toward zero at the middle of channel. The doping distribution at source side of channel reduces the drain induced barrier lowering (DIBL) and the drain side suppresses the band to band tunneling effect. In addition, broadening the doping throughout the channel increases the recombination of electrons and holes and acts as an additional factor for improving the band to band tunneling. Simulation results show that applying this structure on CNTFET enhances the device performance. In comparison with double halo structure with equal saturation current, the proposed GDH structure shows better characteristics and short channel parameters. Furthermore, the delay and power delay product (PDP) analysis versus on/off current ratio shows the efficiency of the proposed GDH structure.     

Improvement in the electrical performance and bias-stress stability of dual-active-layered silicon zinc oxide/zinc oxide thin-film transistor

Si-doped zinc oxide(SZO) thin films are deposited by using a co-sputtering method,and used as the channel active layers of ZnO-based TFTs with single and dual active layer structures.The effects of silicon content on the optical transmittance of the SZO thin film and electrical properties of the SZO TFT are investigated.Moreover,the electrical performances and bias-stress stabilities of the single- and dual-active-layer TFTs are investigated and compared to reveal the effects of the Si doping and dual-active-layer structure.The average transmittances of all the SZO films are about 90% in the visible light region of 400 nm-800 nm,and the optical band gap of the SZO film gradually increases with increasing Si content.The Si-doping can effectively suppress the grain growth of ZnO,revealed by atomic force microscope analysis.Compared with that of the undoped ZnO TFT,the off-state current of the SZO TFT is reduced by more than two orders of magnitude and it is 1.5 × 10~(-12) A,and thus the on/off current ratio is increased by more than two orders of magnitude.In summary,the SZO/ZnO TFT with dual-active-layer structure exhibits a high on/off current ratio of 4.0 × 10~6 and superior stability under gate-bias and drain-bias stress.     

High-performance amorphous In-Ga-Zn-O thin-film transistor nonvolatile memory with a novel p-SnO/n-SnO2 heterojunction charge trapping stack

Amorphous In-Ga-Zn-O (a-IGZO) thin-film transistor (TFT) memories with novel p-SnO/n-SnO₂ heterojunction charge trapping stacks (CTSs) are investigated comparatively under a maximum fabrication temperature of 280 ℃. Compared to a single p-SnO or n-SnO₂ charge trapping layer (CTL), the heterojunction CTSs can achieve electrically programmable and erasable characteristics as well as good data retention. Of the two CTSs, the tunneling layer/p-SnO/n-SnO₂/blocking layer architecture demonstrates much higher program efficiency, more robust data retention, and comparably superior erase characteristics. The resulting memory window is as large as 6.66 V after programming at 13 V/1 ms and erasing at -8 V/1 ms, and the ten-year memory window is extrapolated to be 4.41 V. This is attributed to shallow traps in p-SnO and deep traps in n-SnO₂, and the formation of a built-in electric field in the heterojunction.     

100kV/2A三相恒流重复频率充电装置

 介绍了自行研制的一台100kV/2A三相恒流重复频率充电装置,其恒流电源采用三相L C变换器，6只绝缘栅双极性晶体管并联作为短路器件控制充电停止，可编程序控制器是控制单元的核心。该装置用于重复频率开关实验，充电电流2A，最高充电电压100kV，重复频率10Hz，充电电容1μF，以脉冲串的方式连续运行，工作稳定。