Non-depletion floating layer in SOI LDMOS for enhancing breakdown voltage and eliminating back-gate bias effect

A non-depletion floating layer silicon-on-insulator (NFL SOI) lateral double-diffused metal-oxide-semiconductor (LDMOS) is proposed and the NFL-assisted modulated field (NFLAMF) principle is investigated in this paper. Based on this principle, the floating layer can pin the potential for modulating bulk field. In particular, the accumulated high concentration of holes at the bottom of the NFL can efficiently shield the electric field of the SOI layer and enhance the dielectric field in the buried oxide layer (BOX). At variation of back-gate bias, the shielding charges of NFL can also eliminate back-gate effects. The simulated results indicate that the breakdown voltage (BV) is increased from 315 V to 558 V compared to the conventional reduced surface field (RESURF) SOI (CSOI) LDMOS, yielding a 77% improvement. Furthermore, due to the field shielding effect of the NFL, the device can maintain the same breakdown voltage of 558 V with a thinner BOX to resolve the thermal problem in an SOI device.     

Compound buried layer SOI high voltage device with a step buried oxide

A silicon-on-insulator (SOI) high performance lateral double-diffusion metal oxide semiconductor (LDMOS) on a compound buried layer (CBL) with a step buried oxide (SBO CBL SOI) is proposed.The step buried oxide locates holes in the top interface of the upper buried oxide (UBO) layer.Furthermore,holes with high density are collected in the interface between the polysilicon layer and the lower buried oxide (LBO) layer.Consequently,the electric fields in both the thin LBO and the thick UBO are enhanced by these holes,leading to an improved breakdown voltage.The breakdown voltage of the SBO CBL SOI LDMOS increases to 847 V from the 477 V of a conventional SOI with the same thicknesses of SOI layer and the buried oxide layer.Moreover,SBO CBL SOI can also reduce the self-heating effect.     

A novel partial silicon on insulator high voltage LDMOS with low-k dielectric buried layer

A novel partial silicon-on-insulator (PSOI) high voltage device with a low-k (relative permittivity) dielectric buried layer (LK PSOI) and its breakdown mechanism are presented and investigated by MEDICI.At a low k value the electric field strength in the dielectric buried layer (E I) is enhanced and a Si window makes the substrate share the vertical drop,resulting in a high vertical breakdown voltage;in the lateral direction,a high electric field peak is introduced at the Si window,which modulates the electric field distribution in the SOI layer;consequently,a high breakdown voltage (BV) is obtained.The values of EI and BV of LK PSOI with kI=2 on a 2 μm thick SOI layer over 1 μm thick buried layer are enhanced by 74% and 19%,respectively,compared with those of the conventional PSOI.Furthermore,the Si window also alleviates the self-heating effect.     

A novel P-channel SOI LDMOS structure with non-depletion potential-clamped layer

A novel structure is proposed for doubling the vertical breakdown voltage of silicon-on-insulator(SOI) devices. In this new structure, the conventional buried oxide(BOX) in an SOI device is split into two sections: the source-section BOX and the drain-section BOX. A highly-doped Si layer, referred to as a non-depletion potential-clamped layer(NPCL), is positioned under and close to the two BOX sections. In the split BOXes and the Si region above the BOXes, the blocking voltage(BV) is divided into two parts by the NPCL. The voltage in the NPCL is clamped to be nearly half of the drain voltage. When the drain voltage approaches a breakdown value, the voltage sustained by the source-section BOX and the Si region under the source are nearly the same as the voltage sustained by the drain-section BOX and the Si region under the drain. The vertical BV is therefore almost doubled. The effectiveness of this new structure was verified for a P-channel SOI lateral double-diffused metal-oxide semiconductor(LDMOS) and can be applied to other high-voltage SOI devices. The simulation results show that the BV in an NPCL P-channel SOI LDMOS is improved by 55% and the specific on-resistance(Ron,sp) is reduced by 69% in comparison to the conventional structure.     

A novel high performance TFS SJ IGBT with a buried oxide layer

A novel high performance trench field stop(TFS) superjunction(SJ) insulated gate bipolar transistor(IGBT) with a buried oxide(BO) layer is proposed in this paper. The BO layer inserted between the P-base and the SJ drift region acts as a barrier layer for the hole-carrier in the drift region. Therefore, conduction modulation in the emitter side of the SJ drift region is enhanced significantly and the carrier distribution in the drift region is optimized for the proposed structure. As a result, compared with the conventional TFS SJ IGBT(Conv-SJ), the proposed BO-SJ IGBT structure possesses a drastically reduced on-state voltage drop(Vce(on)) and an improved tradeoff between Vce(on)and turn-off loss(Eoff), with no breakdown voltage(BV) degraded. The results show that with the spacing between the gate and the BO layer Wo = 0.2 μm, the thickness of the BO layer Lo = 0.2 μm, the thickness of the drift region Ld = 90 μm, the half width and doping concentration of the N- and P-pillars Wn = Wp = 2.5 μm and Nn = Np = 3 × 1015cm-3, the Vce(on)and Eoffof the proposed structure are 1.08 V and 2.81 mJ/cm2with the collector doping concentration Nc = 1×1018cm-3and 1.12 V and1.73 mJ/cm2with Nc = 5 × 1017cm-3, respectively. However, with the same device parameters, the Vce(on)and Eofffor the Conv-SJ are 1.81 V and 2.88 mJ/cm2with Nc = 1 × 1018cm-3and 1.98 V and 2.82 mJ/cm2with Nc = 5 × 1017cm-3,respectively. Meanwhile, the BV of the proposed structure and Conv-SJ are 1414 V and 1413 V, respectively.     

A new analytical model for the surface electric field distribution and breakdown voltage of the SOI trench LDMOS

A new analytical model for the surface electric field distribution and breakdown voltage of the silicon on insulator (SOI) trench lateral double-diffused metal-oxide-semiconductor (LDMOS) is presented. Based on the two-dimensional Laplace solution and Poisson solution, the model considers the influence of structure parameters such as the doping concentration of the drift region, and the depth and width of the trench on the surface electric field. Further, a simple analytical expression of the breakdown voltage is obtained, which offers an effective way to gain an optimal high voltage. All the analytical results are in good agreement with the simulation results.     

Low on-resistance high-voltage lateral double-diffused metal oxide semiconductor with a buried improved super-junction layer

A novel low specific on-resistance （Ron,sp） lateral double-diffused metal oxide semiconductor （LDMOS） with a buried improved super-junction （BISJ） layer is proposed. A super-junction layer is buried in the drift region and the P pillar is split into two parts with different doping concentrations. Firstly, the buried super-junction layer causes the multiple-direction assisted depletion effect. The drift region doping concentration of the BISJ LDMOS is therefore much higher than that of the conventional LDMOS. Secondly, the buried super-junction layer provides a bulk low on-resistance path. Both of them reduce Ron,sp greatly. Thirdly, the electric field modulation effect of the new electric field peak introduced by the step doped P pillar improves the breakdown voltage （BV）. The BISJ LDMOS exhibits a BV of 300 V and Ron,sp of 8.08 mΩ·cm2 which increases BV by 35% and reduces Ron,sp by 60% compared with those of a conventional LDMOS with a drift length of 15 μm, respectively.     

A novel LDMOS with a junction field plate and a partial N-buried layer

A novel lateral double-diffused metal–oxide semiconductor (LDMOS) with a high breakdown voltage (BV) and low specific on-resistance (R_on.sp) is proposed and investigated by simulation. It features a junction field plate (JFP) over the drift region and a partial N-buried layer (PNB) in the P-substrate. The JFP not only smoothes the surface electric field (E-field), but also brings in charge compensation between the JFP and the N-drift region, which increases the doping concentration of the N-drift region. The PNB reshapes the equipotential contours, and thus reduces the E-field peak on the drain side and increases that on the source side. Moreover, the PNB extends the depletion width in the substrate by introducing an additional vertical diode, resulting in a significant improvement on the vertical BV. Compared with the conventional LDMOS with the same dimensional parameters, the novel LDMOS has an increase in BV value by 67.4%, and a reduction in R_on.sp by 45.7% simultaneously.     

Novel Indium Arsenide double gate and gate all around nanowire MOSFETs for diminishing the exchange correlation effect: A quantum study

In this paper we present novel double gate (DG) metal oxide semiconductor field effect transistor (MOSFET) and gate all around (GAA) nanowire metal oxide semiconductor field effect transistor (NWT) with a diminished exchange-correlation (Ex-Corr) effect. The key idea in this work is to use Indium Arsenide (InAs) semiconductor instead of Si. We have evaluated and compared different parameters of DG-MOSFET and GAA-NWTs such as threshold voltage, sub-threshold slope, drain induced barrier lowering and ON and OFF state currents from quantum view. Quantum mechanical transport approach based on non-equilibrium green’s function (NEGF) has been performed in the frame work of effective mass theory in consideration with Ex-Corr effect. This simulation method consists of three dimensional Poisson’s equation in which a Schrodinger equation is first solved in each slice of the device to find Eigen energies and Eigen functions. Then, a transport equation of electrons moving in the sub-bands is solved. This fully quantum method treats such effects as source-to-drain tunneling, ballistic transport, and quantum confinement on equal footing. The results show that only a few lowest Eigen sub-bands are occupied and the upper sub-bands can be safely neglected. Also, the interaction between electrons and Ex-Corr effect is diminished in the proposed structure.     

Investigation of laterally single-diffused metal oxide semiconductor (LSMOS) field effect transistor

We propose a distinct approach to implement a laterally single diffused metal-oxide-semiconductor (LSMOS) FET with only one impurity doped p-n junction. In the LSMOS, a single p-n junction is first created using lateral dopant diffusion. The channel is formed in the p region of the p-n junction and the n region acts as the drift region. Two distinct metals of different work function are used to form the “n⁺” source/drain regions and “p⁺” body contact using the charge plasma concept. We demonstrate that the LSMOS is similar in performance to a laterally double diffused metal-oxide-semiconductor (LDMOS) although it has only one impurity doped p-n junction. The LSMOS exhibits a breakdown voltage of ∼50.0 V, an average ON-resistance of 48.7 mΩ-mm² and a peak transconductance of 53.6 μS/μm similar to that of a comparable LDMOS.