阶梯氧化层新型折叠硅横向双扩散功率器件

为了设计功率集成电路所需的低功耗横向功率器件, 提出了一种具有阶梯氧化层折叠硅横向双扩散金属-氧化物-半导体(step oxide folding LDMOS, SOFLDMOS)新结构. 这种结构将阶梯氧化层覆盖在具有周期分布的折叠硅表面, 利用阶梯氧化层的电场调制效应, 通过在表面电场分布中引入新的电场峰而使表面电场分布均匀, 提高了器件的耐压范围, 解决了文献提出的折叠积累型横向双扩散金属-氧化物-半导体器件击穿电压受限的问题. 通过三维仿真软件ISE分析获得, SOFLDMOS 结构打破了硅的极限关系, 充分利用了电场调制效应、多数载流子积累和硅表面导电区倍增效应, 漏极饱和电流比一般LDMOS 提高3.4倍左右, 可以在62 V左右的反向击穿电压条件下, 获得0.74 mΩ·cm²超低的比导通电阻, 远低于传统LDMOS相同击穿电压下2.0 mΩ·cm²比导通电阻, 为实现低压功率集成电路对低功耗横向功率器件的要求提供了一种可选的方案.     

新型缓冲层分区电场调制横向双扩散超结功率器件

为了突破传统横向双扩散金属-氧化物-半导体器件(lateral double-diffused MOSFET)击穿电压与比导通电阻的极限关系,本文在缓冲层横向双扩散超结功率器件(super junction LDMOS-SJ LDMOS)结构基础上,提出了具有缓冲层分区新型SJ-LDMOS结构.新结构利用电场调制效应将分区缓冲层产生的电场峰引入超结(super junction)表面而优化了SJ-LDMOS的表面电场分布,缓解了横向LDMOS器件由于受纵向电场影响使横向电场分布不均匀、横向单位耐压量低的问题.利用仿真分析软件ISE分析表明,优化条件下,当缓冲层分区为3时,提出的缓冲层分区SJ-LDMOS表面电场最优,击穿电压达到饱和时较一般LDMOS结构提高了50%左右,较缓冲层SJ-LDMOS结构提高了32%左右,横向单位耐压量达到18.48 V/μm.击穿电压为382 V的缓冲层分区SJ-LDMOS,比导通电阻为25.6 mΩ·cm2,突破了一般LDMOS击穿电压为254 V时比导通电阻为71.8 mΩ·cm2的极限关系.     

具有超低比导通电阻的双漂移区双导通路径新型横向双扩散金属氧化物半导体

本文提出了一种具有双漂移区和双导通路径的新型横向双扩散金属氧化物半导体（LDMOS）器件,实现了超低比导通电阻(R_on,sp).其漂移区采用P型和N型纵向交替所构成的双漂移区结构,并引入平面栅和槽型栅分别控制P型和N型漂移区,使得器件能够在漂移区中形成两条独立的电子导通或消失路径.在对平面栅施加正向电压时,可使P型漂移区的表面发生反型,形成连接沟道和N+漏极的高浓度电子反型层,从而极大提高器件导通时的电子密度,降低比导通电阻.槽型栅极的引入可使器件在关断时产生一条额外的电子消失路径,从而缩短器件的关断时间(t_off).此外,由于引入P型漂移区,使得电子在P型漂移区内输运时与其体内的空穴发生复合,从而加快了电子的消失过程并进一步地缩短器件的t_off.仿真结果表明,在200 V的击穿电压（BV）等级下,本文所提出的新型LDMOS的R_on,sp为3.43 mΩ·cm²,关断时间为9 ns.相比传统的LDMOS器件, R_on,sp和t_off分别下降了90%和11.6%.该器件不仅实现了R_on,sp和BV的良好折中,而且缩短了器件的t_off,展现出了优异的器件性能.     

具有纵向漏极场板的低导通电阻绝缘体上硅横向双扩散金属氧化物半导体器件新结构

为降低绝缘体上硅(SOI)横向双扩散金属氧化物半导体(LDMOS)器件的导通电阻,同时提高器件击穿电压,提出了一种具有纵向漏极场板的低导通电阻槽栅槽漏SOI-LDMOS器件新结构.该结构特征为采用了槽栅槽漏结构,在纵向上扩展了电流传导区域,在横向上缩短了电流传导路径,降低了器件导通电阻;漏端采用了纵向漏极场板,该场板对漏端下方的电场进行了调制,从而减弱了漏极末端的高电场,提高了器件的击穿电压.利用二维数值仿真软件MEDICI对新结构与具有相同器件尺寸的传统SOI结构、槽栅SOI结构、槽栅槽漏SOI结构进行了比较.结果表明:在保证各自最高优值的条件下,与这三种结构相比,新结构的比导通电阻分别降低了53%,23%和提高了87%,击穿电压则分别提高了4%、降低了9%、提高了45%.比较四种结构的优值,具有纵向漏极场板的槽栅槽漏SOI结构优值最高,这表明在四种结构中新结构保持了较低导通电阻,同时又具有较高的击穿电压.     

具有高开启/关断电流比的Al2O3/AlGaN/GaN金属氧化物半导体高电子迁移率晶体管

采用原子层淀积(ALD)方法,制备了Al₂O₃为栅介质的高性能AlGaN/GaN金属氧化物半导体高电子迁移率晶体管(MOS-HEMT)。在栅压为-20 V时,MOS-HEMT的栅漏电比Schottky-gate HEMT的栅漏电低4个数量级以上。在栅压为+2 V时,Schottky-gate HEMT的栅漏电为191μA;在栅压为+20 V时,MOS-HEMT的栅漏电仅为23.6 nA,比同样尺寸的Schottky-gate HEMT的栅漏电低将近7个数量级。AlGaN/GaN MOS-HEMT的栅压摆幅达到了±20 V。在栅压V_gs=0 V时, MOS-HEMT的饱和电流密度达到了646 mA/mm,相比Schottky-gate HEMT的饱和电流密度(277 mA/mm)提高了133%。栅漏间距为10μm的AlGaN/GaN MOS-HEMT器件在栅压为+3 V时的最大饱和输出电流达到680 mA/mm,特征导通电阻为1.47 mΩ·cm²。Schottky-gate HEMT的开启与关断电流比仅为10⁵,MOS-HEMT的开启与关断电流比超过了10⁹,超出了Schottky-gate HEMT器件4个数量级,原因是栅漏电的降低提高了MOS-HEMT的开启与关断电流比。在V_gs=-14 V时,栅漏间距为10μm的AlGaN/GaN MOS-HEMT的关断击穿电压为640 V,关断泄露电流为27μA/mm。     

具有N型缓冲层REBULF Super Junction LDMOS

针对功率集成电路对低损耗LDMOS (lateral double-diffused MOSFET)类器件的要求,在N型缓冲层super junction LDMOS (buffered SJ-LDMOS)结构基础上, 提出了一种具有N型缓冲层的REBULF (reduced BULk field) super junction LDMOS结构. 这种结构不但消除了N沟道SJ-LDMOS由于P型衬底带来的衬底辅助耗尽效应问题, 使super junction的N区和P区电荷完全补偿, 而且同时利用REBULF的部分N型缓冲层电场调制效应, 在表面电场分布中引入新的电场峰而使横向表面电场分布均匀, 提高了器件的击穿电压. 通过优化部分N型埋层的位置和参数, 利用仿真软件ISE分析表明, 新型REBULF SJ-LDMOS 的击穿电压较一般LDMOS提高了49%左右, 较文献提出的buffered SJ-LDMOS结构提高了30%左右.关键词：lateral double-diffused MOSFETsuper junction击穿电压表面电场     

Low on-resistance high-voltage lateral double-diffused metal oxide semiconductor with a buried improved super-junction layer

A novel low specific on-resistance （Ron,sp） lateral double-diffused metal oxide semiconductor （LDMOS） with a buried improved super-junction （BISJ） layer is proposed. A super-junction layer is buried in the drift region and the P pillar is split into two parts with different doping concentrations. Firstly, the buried super-junction layer causes the multiple-direction assisted depletion effect. The drift region doping concentration of the BISJ LDMOS is therefore much higher than that of the conventional LDMOS. Secondly, the buried super-junction layer provides a bulk low on-resistance path. Both of them reduce Ron,sp greatly. Thirdly, the electric field modulation effect of the new electric field peak introduced by the step doped P pillar improves the breakdown voltage （BV）. The BISJ LDMOS exhibits a BV of 300 V and Ron,sp of 8.08 mΩ·cm2 which increases BV by 35% and reduces Ron,sp by 60% compared with those of a conventional LDMOS with a drift length of 15 μm, respectively.     

High-voltage super-junction lateral double-diffused metal-oxide semiconductor with a partial lightly doped pillar

A novel super-junction lateral double-diffused metal-oxide semiconductor(SJ-LDMOS) with a partial lightly doped P pillar(PD) is proposed.Firstly,the reduction in the partial P pillar charges ensures the charge balance and suppresses the substrate-assisted depletion effect.Secondly,the new electric field peak produced by the P/P-junction modulates the surface electric field distribution.Both of these result in a high breakdown voltage(BV).In addition,due to the same conduction paths,the specific on-resistance(R on,sp) of the PD SJ-LDMOS is approximately identical to the conventional SJ-LDMOS.Simulation results indicate that the average value of the surface lateral electric field of the PD SJ-LDMOS reaches 20V/μm at a 15μm drift length,resulting in a BV of 300V.     

A low specific on-resistance SOI MOSFET with dual gates and a recessed drain

A low specific on-resistance(Ron,sp) integrable silicon-on-insulator(SOI) metal-oxide semiconductor field-effect transistor(MOSFET) is proposed and investigated by simulation.The MOSFET features a recessed drain as well as dual gates,which consist of a planar gate and a trench gate extended to the buried oxide layer(BOX)(DGRD MOSFET).First,the dual gates form dual conduction channels,and the extended trench gate also acts as a field plate to improve the electric field distribution.Second,the combination of the trench gate and the recessed drain widens the vertical conduction area and shortens the current path.Third,the P-type top layer not only enhances the drift doping concentration but also modulates the surface electric field distributions.All of these sharply reduce Ron,sp and maintain a high breakdown voltage(BV).The BV of 233 V and Ron,sp of 4.151 mΩ·cm2(VGS = 15 V) are obtained for the DGRD MOSFET with 15-μm half-cell pitch.Compared with the trench gate SOI MOSFET and the conventional MOSFET,Ron,sp of the DGRD MOSFET decreases by 36% and 33% with the same BV,respectively.The trench gate extended to the BOX synchronously acts as a dielectric isolation trench,simplifying the fabrication processes.     

具有P型覆盖层新型超级结横向双扩散功率器件

为了设计功率集成电路所需要的低功耗横向双扩散金属氧化物半导体器件(lateral double-diffused MOSFET), 在已有的N型缓冲层超级结LDMOS(N-buffered-SJ-LDMOS)结构基础上, 提出了一种具有P型覆盖层新型超级结LDMOS结构(P-covered-SJ-LDMOS). 这种结构不但能够消除传统的N沟道SJ-LDMOS由于P型衬底产生的衬底辅助耗尽问题, 使得超级结层的N区和P区的电荷完全补偿, 而且还能利用覆盖层的电荷补偿作用, 提高N型缓冲层浓度, 从而降低了器件的比导通电阻. 利用三维仿真软件ISE分析表明, 在漂移区长度均为10 μm的情况下, P-covered-SJ-LDMOS的比导通电阻较一般SJ-LDMOS结构降低了59%左右, 较文献提出的N型缓冲层 SJ-LDMOS(N-buffered-SJ-LDMOS)结构降低了43%左右.