The study of crack tip stress and strain field in elasto-plastic materials

Making use of the elastic-plastic finite element program and the small scale yielding crack tip solution, three point bend and compact tension specimens are analysed at various levels of work hardening. Special attention is given to the singular stress distribution at a crack tip, to the fracture behaviour characterized by path independent integral and by crack tip opening displacement. Comparison is made between experimental and theoretical results for a structural low alloy steel. Correlation between the two is satisfactory, the experimental data are bounded by plane strain and plane stress solutions. It is indicated that the uncertainty in the true stress-strain curve in the region of initial yield may strongly influence the theoretical calculations.The authors would like to thank Professor Dr. H.Bethge, director of the Institute of Solid State Physics and Electron Microscopy in Halle (GDR) and Professor Dr. P.Ry, director of the Institute of Physical Metallurgy, Czechoslovak Academy of Sciences in Brno for their support of this cooperative research project.     

MOSFET调制器的实验研究

 介绍了MOSFET调制器的基本原理,并对其并联分流和感应叠加两种开关结构进行了实验研究。基于可编辑逻辑器件设计了其触发电路,驱动电路采用高速MOSFET对管组成的推挽输出形式,加快了MOSFET的开关速度。利用Pspice软件对开关上有无剩余电流电路(RCD)两种情况进行仿真,结果表明,加装RCD电路可以有效吸收MOSFET在关断瞬间产生的反峰电压。实验中,电流波形用Pearson线圈测量,用3个MOSFET并联作开关,当电容充电电压为450 V,负载为30 Ω时,脉冲电流13 A,前沿20 ns,平顶约80 ns;用3个单元调制器感应叠加,当电容充电电压为450 A,负载为30 Ω时,脉冲电流强度为40 A,前沿25 ns,平顶约70 ns。     

MOSFET调制器的实验研究

介绍了MOSFET调制器的基本原理,并对其并联分流和感应叠加两种开关结构进行了实验研究。基于可编辑逻辑器件设计了其触发电路,驱动电路采用高速MOSFET对管组成的推挽输出形式,加快了MOSFET的开关速度。利用Pspice软件对开关上有无剩余电流电路(RCD)两种情况进行仿真,结果表明,加装RCD电路可以有效吸收MOSFET在关断瞬间产生的反峰电压。实验中,电流波形用Pearson线圈测量,用3个MOSFET并联作开关,当电容充电电压为450 V,负载为30 Ω时,脉冲电流13 A,前沿20 ns,平顶约80 ns;用3个单元调制器感应叠加,当电容充电电压为450 A,负载为30 Ω时,脉冲电流强度为40 A,前沿25 ns,平顶约70 ns。     

High-voltage SOI lateral MOSFET with a dual vertical field plate

A new silicon-on-insulator(SOI)power lateral MOSFET with a dual vertical field plate(VFP)in the oxide trench is proposed.The dual VFP modulates the distribution of the electric field in the drift region,which enhances the internal field of the drift region and increases the drift doping concentration of the drift region,resulting in remarkable improvements in breakdown voltage(BV)and specific on-resistance(Ron,sp).The mechanism of the VFP is analyzed and the characteristics of BV and Ron,spare discussed.It is shown that the BV of the proposed device increases from 389 V of the conventional device to 589 V,and the Ron,sp decreases from 366 m·cm2to 110 m·cm2.     

Tight-binding study of quantum transport in nanoscale GaAs Schottky MOSFET

This paper explores the band structure effect to elucidate the feasibility of an ultra-scaled GaAs Schottky MOSFET (SBFET) in a nanoscale regime. We have employed a 20-band sp3d5s* tight-binding (TB) approach to compute E K dispersion. The considerable difference between the extracted effective masses from the TB approach and bulk values implies that quantum confinement affects the device performance. Beside high injection velocity, the ultra-scaled GaAs SBFET suffers from a low conduction band DOS in the Γ valley that results in serious degradation of the gate capacitance. Quantum confinement also results in an increment of the effective Schottky barrier height (SBH). Enhanced Schottky barriers form a double barrier potential well along the channel that leads to resonant tunneling and alters the normal operation of the SBFET. Major factors that may lead to resonant tunneling are investigated. Resonant tunneling occurs at low temperatures and low drain voltages, and gradually diminishes as the channel thickness and the gate length scale down. Accordingly, the GaAs (100) SBFET has poor ballistic performance in nanoscale regime.     

Simulation study of semi-superjunction power MOSFET with SiGe pillar

The feasibility of applying the semi-superjunction (Semi-SJ) with SiGe-pillar (SGP) concept to Power MOSFET is studied in this paper. The electrical performances of SGP are compared with the conventional Power MOSFET through 3D device simulation work in terms of specific-on resistance (_Ron)$\left(R_{on}\right)$, breakdown-voltage (BV  ), the effect to change the Ge mole fraction in the SGP and the thermal stabilization. The results show that the _Ron$R_{on}$ is reduced by 44% on the base of BVs   reducing only 4.8%, tradeoff _Ron$R_{on}$ vs. BV and thermal stabilization of SGP are superior to that of conventional Semi-SJ since the strain effect inducing into the SGP structure in the low power device application.     

Strain relaxation in nano-patterned strained-Si/SiGe heterostructure on insulator

In order to evaluate the strain stability, arrays of strained Si/SiGe nano-stripes and nano-pillars were fabricated by Electron-Beam Lithography (EBL) and Reactive-Ion Etching (RIE). The strain relaxation in the patterned strained Si on SiGe-on-insulator (SGOI) was investigated by high-resolution UV micro-Raman spectroscopy. The Raman measurements before and after patterning indicate that most of the strain in the top strained Si is maintained until scaling down to 300 nm, and relaxation of <15% is observed in pillars with a dimension of 150 nm × 150 nm. In the nano-patterned heterostructure strained Si/SiGe, the observed relaxation is small, which is mainly attributed to the fully relaxed and dislocation-free SiGe virtual substrate fabricated by modified Ge condensation.     

Finite-element lattice fermions in perturbation theory

A lattice Thirring model is defined using a finite-element differencing scheme. The momentum-space propagator is calculated to second order in the coupling, and it is shown that the form of the ultraviolet divergence as the lattice spacing is taken to zero is identical to that found in continuum perturbation theory. This provides further evidence for the absence of fermion species-doubling present in most other lattice formulations.     

Conductance asymmetry of a slot gate Si‐MOSFET in a strong parallel magnetic field

We report measurements on a Si‐MOSFET sample with a slot in the upper gate, allowing for different electron densities n_1,2 across the slot. The dynamic longitudinal resistance was measured by the standard lock‐in technique, while maintaining a large DC current through the source‐drain channel. We find that the conductance of the sample in a strong parallel magnetic field is asymmetric with respect to the DC current direction. This asymmetry increases with magnetic field. The results are interpreted in terms of electron spin accumulation or depletion near the slot.     

An equivalent circuit characterization of power MOSFET accounting for high field and high frequency effects

An equivalent circuit model for analyzing the AC characteristics of power VDMOS transistors is presented. The model accounts for high field and saturation effects. This is achieved by incorporating dependent voltage and current sources in the device model. Results are given for the AC characteristics of a POLYFET F2001 Power VDMOSFET rated with a drain current of 1.4A, power out of 2.5W at 1GHz. The linear, quasi-saturation and saturation regions of the IV characteristics are accounted for in the analysis. The small signal device parasitics are extracted through s-parameter methods. The s-parameter results were used to extract the frequency dependent parasitics including parasitic capacitances, inductances and transconductances.     

Finite-element theory of transport in ferromagnet-normal metal systems

We formulate a theory of spin dependent transport in an electronic circuit involving ferromagnetic elements with noncollinear magnetization which is based on the conservation of spin and charge current. The theory considerably simplifies the calculation of the transport properties of complicated ferromagnet-normal metal systems. We illustrate the theory by considering a novel three-terminal device.     

高温应变下的晶界湮没机理的晶体相场法研究

应用晶体相场方法研究高温应变下的预熔化晶界位错湮没机理. 结果表明, 原预熔化晶界上的位错在应变作用下发生分离运动, 形成新晶界, 即亚晶界. 该过程的实质是生成了亚晶粒; 亚晶界的迁移过程的本质是亚晶粒长大、吞噬旧晶粒的过程; 亚晶界之间的湮没是亚晶粒完全吞噬旧晶粒过程的结束, 体系转变成为单个晶粒结构. 根据原子密度序参数沿x和y方向的投影值随应变量的变化特征, 可以揭示出高温应变作用下, 预熔化亚晶界相遇湮没的本质是两对极性相反的偶极子位错对发生二次湮没, 该湮没的微观过程是通过位错连续二次滑移湮没而实现的, 其湮没的速率较低温时的湮没速率要小许多.     

再结晶和外力场下第二相析出的相场法模拟

在讨论相场法模拟基本方程的基础上,提出了晶界范围宽度的新概念,解释了相场模拟模型中有序化参数梯度范围的物理意义,论证了晶界范围不是晶界原子错排的宽度,而是界面能和界面元素偏析存在范围的观点.建立了一个模拟合金再结晶的相场模型,提出了一系列法则来获得模型中各参数的物理真实值,以AZ31镁合金为例,实现了再结晶过程晶粒长大的真实时间和空间的模拟,通过与试验数据的对比证明了模型的有效性.此外,还列举了相场法模拟Ti-25Al-10Nb合金中O相在外力场作用下析出过程的一系列有趣的新结果,讨论了外力场对第二相析出的重要影响和机理以及模拟结果对合金开发潜在的重要指导意义. 关键词： 相场法 再结晶 析出 外力场     

Visualizing the strain field in semiflexible polymer networks: strain fluctuations and nonlinear rheology of F-actin gels

We image semiflexible polymer networks under shear at the micrometer scale. By tracking embedded probe particles, we determine the local strain field, and directly measure its uniformity, or degree of affineness, on scales of 2-100 microm. The degree of nonaffine strain depends upon the polymer length and cross-link density, consistent with theoretical predictions. We also find a direct correspondence between the uniformity of the microscale strain and the nonlinear elasticity of the networks in the bulk.     

Effect of gate engineering in JLSRG MOSFET to suppress SCEs: An analytical study

In this work, an analytical model of gate-engineered junctionless surrounding gate MOSFET (JLSRG) has been proposed to uncover its potential benefit to suppress short-channel effects (SCEs). Analytical modelling of centre potential for gate-engineered JLSRG devices has been developed using parabolic approximation method. From the developed centre potential, the parameters like threshold voltage, surface potential, Electric Field, Drain-induced Barrier Lowering (DIBL) and subthershold swing are determined. A nice agreement between the results obtained from the model and TCAD simulation demonstrates the validity and correctness of the model. A comparative study of the efficacy to suppress SCEs for Dual-Material (DM) and Single-Material (SM) junctionless surrounding gate MOSFET of the same dimensions has also been carried out. Result indicates that TM-JLSRG devices offer a noticeable enhancement in the efficacy to suppress SCEs by as compared to SM-JLSRG and DM-JLSRG device structures. The effect of different length ratios of three channel regions related to three different gate materials of TM-JLSRG structure on the SCEs have also been discussed. As a result, we demonstrate that TM-JLSRG device can be considered as a competitive contender to the deep-submicron mainstream MOSFETs for low-power VLSI applications.     

A percolation study of RTS noise in deep sub-micron MOSFET by Monte Carlo simulation

Based on percolation theory and random telegraph signal (RTS) noise generation mechanism, a numerical model for RTS in deep submicron metal-oxide-semiconductor field-effect transistor (MOSFET) was presented, with which the dependence of Tc/Te (where Tc=capture time, Te=emission period ) on energy levels and trap depth with respect to the interface of traps can be simulated. Compared with experimental results, the simulated ones showed a good qualitative agreement.     

6H-SiC肖特基源漏MOSFET的模拟仿真研究

给出了一种新型SiC MOSFET——6H-SiC肖特基源漏MOSFET.这种器件结构制备工艺简单，避 免了长期困扰常规SiC MOSFET的离子注入工艺难度大、退火温度高、晶格损伤大，注入激活 率低等问题.分析了该器件的电流输运机理，并通过MEDICI模拟，给出了SiC肖特基源漏MOSF ET伏安特性以及其和金属功函数、栅氧化层厚度和栅长关系. 关键词： 碳化硅 肖特基接触 MOSFET 势垒高度     

Finite-element analysis of planar dielectric waveguide discontinuities

The finite element method is combined with the mode-matching method and the multi-mode network method to analyze the scattering and radiation characteristics of a class of planar dielectric waveguide discontinuities. Unlike the conventional method to treat the radiation as a source-field problem, in the present approach, the dispersion characteristics of dielectric guided-wave structures are calculated first, and then the radiation problem is transferred to the propagation problem of a series of surface-waves and space waves from the viewpoint of scattering, thus the analysis is tremendously simplified.