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 共查询到19条相似文献,搜索用时 93 毫秒
1.
花磊  宋国峰  郭宝山  汪卫敏  张宇 《物理学报》2008,57(11):7210-7215
理论研究了平面电磁波通过n型重掺GaAs薄膜的透射谱.当GaAs薄膜两表面刻上亚波长的周期性沟槽结构时,透射谱在中红外波段出现了异常的透射增强现象.把这一现象归因于表面等离子体模式和波导模式的耦合.通过优化结构参数可以得到最大的透射效率.此外,发现随着掺杂浓度的升高,透射谱线中的透射峰逐渐向高频方向移动,最优化后透射峰值随掺杂浓度的升高而逐渐降低.这是由于掺杂浓度的改变,导致了不同的等离子体频率和电子碰撞频率,从而影响了激发模式和薄膜对电磁波的吸收. 关键词: 表面等离子体 掺杂半导体 增强透射 掺杂调制  相似文献   

2.
掺杂稀土离子发光动力学模型   总被引:1,自引:0,他引:1       下载免费PDF全文
马义  闫阔  杨波  夏上达 《物理学报》1999,48(7):1361-1371
研究了发光体系中能量传递对发光时间演化的影响.针对以往各种能量传递模型中存在的问题,同时考虑施主-受主(D-A)能量传递和施主-施主(D-D)能量迁移,将只考虑D-A能量传递的I-H,D-H,V-F模型与考虑到D-D能量迁移的跳跃模型B分别结合起来,建立了I-H-B,D-H-B,V-F-B三种综合模型.采用这些模型对钾冰晶石(elpasolite)体系的施主发光激发态占据概率进行数值模拟,给出不同D、A浓度下及不同D-A,D-D作用强度条件下施主发光的时间演化曲线,发现V-F-B模型给出的曲线最合理.然后 关键词:  相似文献   

3.
李聪  庄奕琪  韩茹  张丽  包军林 《物理学报》2012,61(7):78504-078504
为抑制短沟道效应和热载流子效应, 提出了一种非对称HALO掺杂栅交叠轻掺杂漏围栅MOSFET新结构. 通过在圆柱坐标系中精确求解三段连续的泊松方程, 推导出新结构的沟道静电势、阈值电压以及亚阈值电流的解析模型. 结果表明, 新结构可有效抑制短沟道效应和热载流子效应, 并具有较小的关态电流. 此外, 分析还表明栅交叠区的掺杂浓度对器件的亚阈值电流几乎没有影响, 而栅电极功函数对亚阈值电流的影响较大. 解析模型结果和三维数值仿真工具ISE所得结果高度符合.  相似文献   

4.
赵阳  陈锦泰 《光学学报》1994,14(3):57-263
建立了孤子掺杂光纤放大的半经典模型,给出了分布放大透明传输的泵浦条件,详细讨论了激发态吸收的影响。文中结果为Er^3+掺杂光纤孤子放大器的设计提供了重要理论依据。  相似文献   

5.
双面阶梯埋氧层部分SOI高压器件新结构   总被引:4,自引:0,他引:4       下载免费PDF全文
李琦  张波  李肇基 《物理学报》2008,57(10):6565-6570
提出了双面阶梯埋氧层部分绝缘硅(silicon on insulator,SIO)高压器件新结构. 双面阶梯埋氧层的附加电场对表面电场的调制作用使表面电场达到近似理想的均匀分布, 耗尽层通过源极下硅窗口进一步向硅衬底扩展, 使埋氧层中纵向电场高达常规SOI结构的两倍, 且缓解了常规SOI结构的自热效应. 建立了漂移区电场的二维解析模型, 获得了器件结构参数间的优化关系. 结果表明, 在导通电阻相近的情况下, 双面阶梯埋氧层部分SOI结构击穿电压较常规SOI器件提高58%, 温度降低10—30K. 关键词: 双面阶梯 埋氧层 调制 自热效应  相似文献   

6.
介绍了HL-2A 上基于脉冲步进阶梯调制(PSM)技术的高压电源控制系统的研究。控制系统以数字信号处理+现场可编程门阵列(DSP+FPGA)为架构,控制112 个每秒采样(SPS)模块,按照一定的控制方式使电源输出稳定的电压。DSP 负责数据传输、通讯、控制算法等;FPGA 利用其强大的逻辑功能输出所需的脉冲。通过对程序的编写、仿真和调试,实验结果表明该控制系统的特性达到了设计要求。  相似文献   

7.
研究两种掺杂电致发光器件聚乙烯基咔唑(PVK):Rubrene和Alq3:MN-PPV。通过其光致发光及电致发光特性的研究,发现两种器件的光致发光与电致发光有较大差别。分析认为这是能量传递及电致发光中陷阱对载流子吸引的共同作用使得PVK激子在光致发光和电致发光中的复合速率不同造成的;同时发现对于不同浓度的PVK:Rubrene及Alq3:MN-PPV电致发光随电压增加都发生变色现象,但是它们分别是由两种不同的机制造成的:前者作为染料分子Rubrene,不能形成类似Alq3那样的分相体系,Rubrene发光主要来自PVK的能量传递及陷阱电子对PVK空穴的吸引;后者是由于分相造成载流子在两相中的迁移不平衡。  相似文献   

8.
通过建立和求解指数掺杂阴极中电子所遵循的二维连续性方程,得到了透射式指数掺杂阴极的调制传递函数表达式,并利用该表达式对阴极分辨力特性进行了理论计算和分析.计算结果显示,与均匀掺杂相比,指数掺杂能较明显地提高阴极的分辨力.当空间频率f在100—400 lp/mm范围时,分辨力的提高最为明显,如当f=200 lp/mm时,分辨力一般可提高20%—50%.与量子效率的提高相同,指数掺杂阴极分辨力的提高也是内建电场作用的结果. 关键词: 指数掺杂 内建电场 分辨力 调制传递函数  相似文献   

9.
掺杂PPQ薄膜的电致发光及电场调制   总被引:1,自引:1,他引:1  
从掺杂PPQ薄膜单层器件的电致发光光谱在掺杂前后的变化。说明掺杂PPQ薄膜中存在着基质分子和掺杂分子间的能量传递,其电致发光光谱随加电场变化说明电场对PPQ薄膜的电致发光具有调制作用。用一个由单链模型扩展到包括杂质和外场的Hamiltonian进行数值求解。结果表明:在PPQ和TPL分子之间有效的能量传递是源于它们之间的是荷转移,且随着外加电压的变化,其电致发光谱峰位的移动与掺杂前后系统总量的改变及发光强度与掺杂后转移的电荷数之间分别存在对应关系,这一模型很好地解释了电场对PPQ薄膜电致发光的调制作用。  相似文献   

10.
通过结合准相位匹配理论和空间分布自混频(或自倍频)激光模型提出了稀土掺杂光学超晶格材料自变频激光理论模型,该模型计入了弱聚焦的高斯光束空间分布,泵浦耦合以及非理想周期结构的影响,并应用该理论模型对Nd^3 离子掺杂非理想周期极化铌酸锂(Nd^3 :APLN)晶体同步自变频多波长激光进行了模拟计算,计算结果,尤其是阈值、可见激光总输出功率和同步可见激光谱线相对强度分布等与实验结果符合得很好,从而表明该模型的有效性。  相似文献   

11.
A new analytical model for the surface electric field distribution and breakdown voltage of the silicon on insulator (SOI) trench lateral double-diffused metal-oxide-semiconductor (LDMOS) is presented. Based on the two-dimensional Laplace solution and Poisson solution, the model considers the influence of structure parameters such as the doping concentration of the drift region, and the depth and width of the trench on the surface electric field. Further, a simple analytical expression of the breakdown voltage is obtained, which offers an effective way to gain an optimal high voltage. All the analytical results are in good agreement with the simulation results.  相似文献   

12.
胡夏融  吕瑞 《中国物理 B》2014,(12):548-553
In this paper, an analytical model for the vertical electric field distribution and optimization of a high voltage-reduced bulk field(REBULF) lateral double-diffused metal–oxide-semiconductor(LDMOS) transistor is presented. The dependences of the breakdown voltage on the buried n-layer depth, thickness, and doping concentration are discussed in detail.The REBULF criterion and the optimal vertical electric field distribution condition are derived on the basis of the optimization of the electric field distribution. The breakdown voltage of the REBULF LDMOS transistor is always higher than that of a single reduced surface field(RESURF) LDMOS transistor, and both analytical and numerical results show that it is better to make a thick n-layer buried deep into the p-substrate.  相似文献   

13.
This paper presents a new silicon-on-insulator(SOI) lateral-double-diffused metal-oxide-semiconductor transistor(LDMOST) device with alternated high-k dielectric and step doped silicon pillars(HKSD device). Due to the modulation of step doping technology and high-k dielectric on the electric field and doped profile of each zone, the HKSD device shows a greater performance. The analytical models of the potential, electric field, optimal breakdown voltage, and optimal doped profile are derived. The analytical results and the simulated results are basically consistent, which confirms the proposed model suitable for the HKSD device. The potential and electric field modulation mechanism are investigated based on the simulation and analytical models. Furthermore, the influence of the parameters on the breakdown voltage(BV) and specific on-resistance(Ron,sp) are obtained. The results indicate that the HKSD device has a higher BV and lower Ron,sp compared to the SD device and HK device.  相似文献   

14.
郑直  李威  李平 《中国物理 B》2013,(4):471-475
A non-depletion floating layer silicon-on-insulator (NFL SOI) lateral double-diffused metal-oxide-semiconductor (LDMOS) is proposed and the NFL-assisted modulated field (NFLAMF) principle is investigated in this paper. Based on this principle, the floating layer can pin the potential for modulating bulk field. In particular, the accumulated high concentration of holes at the bottom of the NFL can efficiently shield the electric field of the SOI layer and enhance the dielectric field in the buried oxide layer (BOX). At variation of back-gate bias, the shielding charges of NFL can also eliminate back-gate effects. The simulated results indicate that the breakdown voltage (BV) is increased from 315 V to 558 V compared to the conventional reduced surface field (RESURF) SOI (CSOI) LDMOS, yielding a 77% improvement. Furthermore, due to the field shielding effect of the NFL, the device can maintain the same breakdown voltage of 558 V with a thinner BOX to resolve the thermal problem in an SOI device.  相似文献   

15.
乔明  庄翔  吴丽娟  章文通  温恒娟  张波  李肇基 《中国物理 B》2012,21(10):108502-108502
Based on the theoretical and experimental investigation of a thin silicon layer(TSL) with linear variable doping(LVD) and further research on the TSL LVD with a multiple step field plate(MSFP),a breakdown voltage(BV) model is proposed and experimentally verified in this paper.With the two-dimensional Poisson equation of the silicon on insulator(SOI) device,the lateral electric field in drift region of the thin silicon layer is assumed to be constant.For the SOI device with LVD in the thin silicon layer,the dependence of the BV on impurity concentration under the drain is investigated by an enhanced dielectric layer field(ENDIF),from which the reduced surface field(RESURF) condition is deduced.The drain in the centre of the device has a good self-isolation effect,but the problem of the high voltage interconnection(HVI) line will become serious.The two step field plates including the source field plate and gate field plate can be adopted to shield the HVI adverse effect on the device.Based on this model,the TSL LVD SOI n-channel lateral double-diffused MOSFET(nLDMOS) with MSFP is realized.The experimental breakdown voltage(BV) and specific on-resistance(R on,sp) of the TSL LVD SOI device are 694 V and 21.3 ·mm 2 with a drift region length of 60 μm,buried oxide layer of 3 μm,and silicon layer of 0.15 μm,respectively.  相似文献   

16.
胡盛东  张波  李肇基  罗小蓉 《中国物理 B》2010,19(3):37303-037303
A new partial-SOI (PSOI) high voltage device structure called a CI PSOI (charge island PSOI) is proposed for the first time in this paper. The device is characterized by a charge island layer on the interface of the top silicon layer and the dielectric buried layer in which a series of equidistant high concentration n+-regions is inserted. Inversion holes resulting from the vertical electric field are located in the spacing between two neighbouring n+-regions on the interface by the force with ionized donors in the undepleted n+-regions, and therefore effectively enhance the electric field of the dielectric buried layer (EI) and increase the breakdown voltage (BV), thereby alleviating the self-heating effect (SHE) by the silicon window under the source. An analytical model of the vertical interface electric field for the CI PSOI is presented and the analytical results are in good agreement with the 2D simulation results. The BV and EI of the CI PSOI LDMOS increase to 631~V and 584~V/μ m from 246~V and 85.8~V/μ m for the conventional PSOI with a lower SHE, respectively. The effects of the structure parameters on the device characteristics are analysed for the proposed device in detail.  相似文献   

17.
Based on the analysis of vertical electric potential distribution across the dual-channel strained p-type Si/strained Si 1-x Ge x /relaxd Si 1-y Ge y (s-Si/s-SiGe/Si 1-y Ge y) metal-oxide-semiconductor field-effect transistor (PMOSFET),an-alytical expressions of the threshold voltages for buried channel and surface channel are presented.And the maximum allowed thickness of s-Si is given,which can ensure that the strong inversion appears earlier in the buried channel (compressive strained SiGe) than in the surface channel (tensile strained Si),because the hole mobility in the buried channel is higher than that in the surface channel.Thus they offer a good accuracy as compared with the results of device simulator ISE.With this model,the variations of threshold voltage and maximum allowed thickness of s-Si with design parameters can be predicted,such as Ge fraction,layer thickness,and doping concentration.This model can serve as a useful tool for p-channel s-Si/s-SiGe/Si 1-y Ge y metal-oxide-semiconductor field-effect transistor (MOSFET) designs.  相似文献   

18.
A new analytical model of high voltage silicon on insulator (SOI) thin film devices is proposed, and a formula of silicon critical electric field is derived as a function of silicon film thickness by solving a 2D Poisson equation from an effective ionization rate, with a threshold energy taken into account for electron multiplying. Unlike a conventional silicon critical electric field that is constant and independent of silicon film thickness, the proposed silicon critical electric field increases sharply with silicon film thickness decreasing especially in the case of thin films, and can come to 141V/μm at a film thickness of 0.1μm which is much larger than the normal value of about 30V/μm. From the proposed formula of silicon critical electric field, the expressions of dielectric layer electric field and vertical breakdown voltage (VB,V) are obtained. Based on the model, an ultra thin film can be used to enhance dielectric layer electric field and so increase vertical breakdown voltage for SOI devices because of its high silicon critical electric field, and with a dielectric layer thickness of 2μm the vertical breakdown voltages reach 852 and 300V for the silicon film thicknesses of 0.1 and 5μm, respectively. In addition, a relation between dielectric layer thickness and silicon film thickness is obtained, indicating a minimum vertical breakdown voltage that should be avoided when an SOI device is designed. 2D simulated results and some experimental results are in good agreement with analytical results.  相似文献   

19.
We present an analytical model for the mode of index-guided microstructured fibers. This model exhibits essential symmetry features of the field unlike the commonly used equivalent step-index (ESI) model. The model is shown to be more accurate than the equivalent step-index (ESI) model in predicting the effective-indices of the mode. Results for the modal effective index, near and far fields and dispersion have been included.  相似文献   

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