One-dimensional breakdown voltage model of SOI RESURF lateral power device based on lateral linearly graded approximation

A novel one-dimensional(1D) analytical model is proposed for quantifying the breakdown voltage of a reduced surface field(RESURF) lateral power device fabricated on silicon on an insulator(SOI) substrate.We assume that the charges in the depletion region contribute to the lateral PN junctions along the diagonal of the area shared by the lateral and vertical depletion regions.Based on the assumption,the lateral PN junction behaves as a linearly graded junction,thus resulting in a reduced surface electric field and high breakdown voltage.Using the proposed model,the breakdown voltage as a function of device parameters is investigated and compared with the numerical simulation by the TCAD tools.The analytical results are shown to be in fair agreement with the numerical results.Finally,a new RESURF criterion is derived which offers a useful scheme to optimize the structure parameters.This simple 1D model provides a clear physical insight into the RESURF effect and a new explanation on the improvement in breakdown voltage in an SOI RESURF device.     

An AlGaN/GaN HEMT with enhanced breakdown and near-zero breakdown voltage temperature coefficient

An AlGaN/GaN high-electron mobility transistor (HEMT) with a novel source-connected air-bridge field plate (AFP) is experimentally verified. The device features a metal field plate that jumps from the source over the gate region and lands between the gate and drain. When compared to a similar size HEMT device with conventional field plate (CFP) structure, the AFP not only minimizes the parasitic gate to source capacitance, but also exhibits higher OFF-state breakdown voltage and one order of magnitude lower drain leakage current. In a device with a gate to drain distance of 6 μm and a gate length of 0.8 μm, three times higher forward blocking voltage of 375 V was obtained at V_GS=-5 V. In contrast, a similar sized HEMT with CFP can only achieve a breakdown voltage no higher than 125 V using this process, regardless of device dimensions. Moreover, a temperature coefficient of 0 V/K for the breakdown voltage is observed. However, devices without field plate (no FP) and with optimized conventional field plate (CFP) exhibit breakdown voltage temperature coefficients of -0.113 V/K and -0.065 V/K, respectively.     

An AlGaN/GaN HEMT with enhanced breakdown and a near-zero breakdown voltage temperature coefficient

An AlGaN/GaN high-electron mobility transistor(HEMT) with a novel source-connected air-bridge field plate(AFP) is experimentally verified.The device features a metal field plate that jumps from the source over the gate region and lands between the gate and drain.When compared to a similar size HEMT device with a conventional field plate(CFP) structure,the AFP not only minimizes the parasitic gate to source capacitance,but also exhibits higher OFF-state breakdown voltage and one order of magnitude lower drain leakage current.In a device with a gate to drain distance of 6 μm and a gate length of 0.8 μm,three times higher forward blocking voltage of 375 V was obtained at VGS =-5 V.In contrast,a similar sized HEMT with a CFP can only achieve a breakdown voltage no higher than 125 V using this process,regardless of device dimensions.Moreover,a temperature coefficient of 0 V/K for the breakdown voltage is observed.However,devices without a field plate(no FP) and with an optimized conventional field plate(CFP) exhibit breakdown voltage temperature coefficients of-0.113 V/K and-0.065 V/K,respectively.     

Compound buried layer SOI high voltage device with a step buried oxide

A silicon-on-insulator (SOI) high performance lateral double-diffusion metal oxide semiconductor (LDMOS) on a compound buried layer (CBL) with a step buried oxide (SBO CBL SOI) is proposed.The step buried oxide locates holes in the top interface of the upper buried oxide (UBO) layer.Furthermore,holes with high density are collected in the interface between the polysilicon layer and the lower buried oxide (LBO) layer.Consequently,the electric fields in both the thin LBO and the thick UBO are enhanced by these holes,leading to an improved breakdown voltage.The breakdown voltage of the SBO CBL SOI LDMOS increases to 847 V from the 477 V of a conventional SOI with the same thicknesses of SOI layer and the buried oxide layer.Moreover,SBO CBL SOI can also reduce the self-heating effect.     

Analytical models of lateral power devices with arbitrary vertical doping profiles in the drift region

By solving the 2D Poisson's equation, analytical models are proposed to calculate the surface potential and electric field distributions of lateral power devices with arbitrary vertical doping profiles. The vertical and the lateral breakdown voltages are formulized to quantify the breakdown characteristic in completely-depleted and partially-depleted cases. A new reduced surface field (RESURF) criterion which can be used in various drift doping profiles is further derived for obtaining the optimal trade-off between the breakdown voltage and the on-resistance. Based on these models and the numerical simulation, the electric field modulation mechanism and the breakdown characteristics of lateral power devices are investigated in detail for the uniform, linear, Gaussian, and some discrete doping profiles along the vertical direction in the drift region. Then, the mentioned vertical doping profiles of these devices with the same geometric parameters are optimized, and the results show that the optimal breakdown voltages and the effective drift doping concentrations of these devices are identical, which are equal to those of the uniform-doped device, respectively. The analytical results of these proposed models are in good agreement with the numerical results and the previous experimental results, confirming the validity of the models presented here.     

A novel thin drift region device with field limiting rings in substrate

A novel thin drift region device with heavily doped N⁺ rings embedded in the substrate is reported, which is called the field limiting rings in substrate lateral double-diffused MOS transistor (SFLR LDMOS). In the SFLR LDMOS, the peak of the electric field at the main junction is reduced due to the transfer of the voltage from the main junction to other field limiting ring junctions, so the vertical electric field is improved significantly. A model of the breakdown voltage is developed, from which optimal spacing is obtained. The numerical results indicate that the breakdown voltage of the device proposed is increased by 76% in comparison to that of the conventional LDMOS.     

Design optimization of high breakdown voltage vertical GaN junction barrier Schottky diode with high-K/low-K compound dielectric structure

A vertical junction barrier Schottky diode with a high-$K$/low-$K$ compound dielectric structure is proposed and optimized to achieve a high breakdown voltage (BV). There is a discontinuity of the electric field at the interface of high-$K$ and low-$K$ layers due to the different dielectric constants of high-$K$ and low-$K$ dielectric layers. A new electric field peak is introduced in the n-type drift region of junction barrier Schottky diode (JBS), so the distribution of electric field in JBS becomes more uniform. At the same time, the effect of electric-power line concentration at the p-n junction interface is suppressed due to the effects of the high-$K$ dielectric layer and an enhancement of breakdown voltage can be achieved. Numerical simulations demonstrate that GaN JBS with a specific on-resistance ($R_{\rm on, sp}$) of 2.07 m$\Omega\cdot$cm$^{2}$ and a BV of 4171 V which is 167% higher than the breakdown voltage of the common structure, resulting in a high figure-of-merit (FOM) of 8.6 GW/cm$^{2}$, and a low turn-on voltage of 0.6 V.     

New SOI power device with multi-region high-concentration fixed interface charge and the model of breakdown voltage

A new SOI power device with multi-region high-concentration fixed charge(MHFC) is reported. The MHFC is formed through implanting Cs or I ion into the buried oxide layer(BOX), by which the high-concentration dynamic electrons and holes are induced at the top and bottom interfaces of BOX. The inversion holes can enhance the vertical electric field and raise the breakdown voltage since the drain bias is mainly generated from the BOX. A model of breakdown voltage is developed, from which the optimal spacing has also been obtained. The numerical results indicate that the breakdown voltage of device proposed is increased by 287% in comparison to that of conventional LDMOS.     

A new analytical model for the surface electric field distribution and breakdown voltage of the SOI trench LDMOS

A new analytical model for the surface electric field distribution and breakdown voltage of the silicon on insulator (SOI) trench lateral double-diffused metal-oxide-semiconductor (LDMOS) is presented. Based on the two-dimensional Laplace solution and Poisson solution, the model considers the influence of structure parameters such as the doping concentration of the drift region, and the depth and width of the trench on the surface electric field. Further, a simple analytical expression of the breakdown voltage is obtained, which offers an effective way to gain an optimal high voltage. All the analytical results are in good agreement with the simulation results.     

An AlGaN/GaN HEMT with reduced surface electric field and improved breakdown voltage

A reduced surface electric field in AlGaN/GaN high electron mobility transistor (HEMT) is investigated by employing a localized Mg-doped layer under the two-dimensional electron gas (2-DEG) channel as an electric field shaping layer. The electric field strength around the gate edge is effectively relieved and the surface electric field is distributed evenly as compared with those of HEMTs with conventional source-connected field plate and double field plate structures with the same device physical dimensions. Compared with the HEMTs with conventional source-connected field plate and double field plate, the HEMT with Mg-doped layer also shows that the breakdown location shifts from the surface of the gate edge to the bulk Mg-doped layer edge. By optimizing both the length of Mg-doped layer, L_m, and the doping concentration, a 5.5 times and 3 times the reduction in the peak electric field near the drain side gate edge is observed as compared with those of the HEMTs with source-connected field plate structure and double field plate structure, respectively. In a device with V_GS=-5 V, L_m=1.5 μm, a peak Mg doping concentration of 8× 10¹⁷ cm^-3 and a drift region length of 10 μm, the breakdown voltage is observed to increase from 560 V in a conventional device without field plate structure to over 900 V without any area overhead penalty.     

高k介质电导增强SOI LDMOS机理与优化设计

本文提出一种高k介质电导增强SOI LDMOS新结构（HK CE SOI LDMOS）,并研究其机理. HK CE SOI LDMOS的特征是在漂移区两侧引入高k介质,反向阻断时,高k介质对漂移区进行自适应辅助耗尽,实现漂移区三维RESURF效应并调制电场,因而提高器件耐压和漂移区浓度并降低导通电阻. 借助三维仿真研究耐压、比导通电阻与器件结构参数之间的关系. 结果表明,HK CE SOI LDMOS与常规超结SOI LDMOS相比,耐压提高16%–18%,同时比导通电阻降低13%–20%,且缓解了由衬底辅助耗尽效应带来的电荷非平衡问题. 关键词： k介质')" href="#">高k介质 绝缘体上硅 (SOI) 击穿电压 比导通电阻     

环槽电极结构的伪火花开关耐压特性

 设计了一种具有环槽电极结构的新型伪火花开关,进行了空气介质下的耐压特性实验,并与传统的同轴多通道结构的伪火花开关耐压特性进行了对比。给出了伪火花开关工作的气压范围（1~100 Pa）和两种伪火花开关的最大耐压。实验结果显示,新型环槽结构伪火花开关最大耐压达到41 V,而传统同轴多通道开关的最大高耐压只有28.4 kV,新设计开关的最大耐压和耐压稳定性都明显高于同轴多通道开关。     

环槽电极结构的伪火花开关耐压特性

设计了一种具有环槽电极结构的新型伪火花开关,进行了空气介质下的耐压特性实验,并与传统的同轴多通道结构的伪火花开关耐压特性进行了对比。给出了伪火花开关工作的气压范围（1~100 Pa）和两种伪火花开关的最大耐压。实验结果显示,新型环槽结构伪火花开关最大耐压达到41 V,而传统同轴多通道开关的最大高耐压只有28.4 kV,新设计开关的最大耐压和耐压稳定性都明显高于同轴多通道开关。     

Effect of gate length on breakdown voltage in AlGaN/GaN high-electron-mobility transistor

The effects of gate length L_G on breakdown voltage VBRare investigated in AlGaN/GaN high-electron-mobility transistors(HEMTs) with L_G= 1 μm~20 μm. With the increase of L_G, VBRis first increased, and then saturated at LG= 3 μm. For the HEMT with L_G= 1 μm, breakdown voltage VBRis 117 V, and it can be enhanced to 148 V for the HEMT with L-_G= 3 μm. The gate length of 3 μm can alleviate the buffer-leakage-induced impact ionization compared with the gate length of 1 μm, and the suppression of the impact ionization is the reason for improving the breakdown voltage.A similar suppression of the impact ionization exists in the HEMTs with LG 3 μm. As a result, there is no obvious difference in breakdown voltage among the HEMTs with LG= 3 μm~20 μm, and their breakdown voltages are in a range of 140 V–156 V.     

An AlGaN/GaN HEMT with a reduced surface electric field and an improved breakdown voltage

A reduced surface electric field in an AlGaN/GaN high electron mobility transistor(HEMT) is investigated by employing a localized Mg-doped layer under the two-dimensional electron gas(2-DEG) channel as an electric field shaping layer.The electric field strength around the gate edge is effectively relieved and the surface electric field is distributed evenly as compared with those of HEMTs with conventional source-connected field plate and double field plate structures with the same device physical dimensions.Compared with the HEMTs with conventional sourceconnected field plates and double field plates,the HEMT with a Mg-doped layer also shows that the breakdown location shifts from the surface of the gate edge to the bulk Mg-doped layer edge.By optimizing both the length of Mg-doped layer,L m,and the doping concentration,a 5.5 times and 3 times the reduction in the peak electric field near the drain side gate edge is observed as compared with those of the HEMTs with source-connected field plate structure and double field plate structure,respectively.In a device with V GS = -5 V,L m = 1.5 μm,a peak Mg doping concentration of 8×10 17cm-3 and a drift region length of 10 μm,the breakdown voltage is observed to increase from 560 V in a conventional device without field plate structure to over 900 V without any area overhead penalty.     

Breakdown voltage model and structure realization of a thin silicon layer with linear variable doping on a silicon on insulator high voltage device with multiple step field plates

Based on the theoretical and experimental investigation of a thin silicon layer(TSL) with linear variable doping(LVD) and further research on the TSL LVD with a multiple step field plate(MSFP),a breakdown voltage(BV) model is proposed and experimentally verified in this paper.With the two-dimensional Poisson equation of the silicon on insulator(SOI) device,the lateral electric field in drift region of the thin silicon layer is assumed to be constant.For the SOI device with LVD in the thin silicon layer,the dependence of the BV on impurity concentration under the drain is investigated by an enhanced dielectric layer field(ENDIF),from which the reduced surface field(RESURF) condition is deduced.The drain in the centre of the device has a good self-isolation effect,but the problem of the high voltage interconnection(HVI) line will become serious.The two step field plates including the source field plate and gate field plate can be adopted to shield the HVI adverse effect on the device.Based on this model,the TSL LVD SOI n-channel lateral double-diffused MOSFET(nLDMOS) with MSFP is realized.The experimental breakdown voltage(BV) and specific on-resistance(R on,sp) of the TSL LVD SOI device are 694 V and 21.3 ·mm 2 with a drift region length of 60 μm,buried oxide layer of 3 μm,and silicon layer of 0.15 μm,respectively.     

具有p-GaN岛状埋层耐压结构的横向AlGaN/GaN高电子迁移率晶体管

GaN基高电子迁移率晶体管(HEMT)相对较低的击穿电压严重限制了其大功率应用.为了进一步改善器件的击穿特性,通过在n-GaN外延缓冲层中引入六个等间距p-GaN岛掩埋缓冲层(PIBL)构成p-n结,提出一种基于p-GaN埋层结构的新型高耐压AlGaN/GaN HEMT器件结构.Sentaurus TCAD仿真结果表明,在关态高漏极电压状态下,p-GaN埋层引入的多个反向p-n结不仅能够有效调制PIBL AlGaN/GaN HEMT的表面电场和体电场分布,而且对于缓冲层泄漏电流有一定的抑制作用,这保证了栅漏间距为10μm的PIBL HEMT能够达到超过1700 V的高击穿电压(BV),是常规结构AlGaN/GaN HEMT击穿电压(580 V)的3倍.同时,PIBL结构AlGaN/GaN HEMT的特征导通电阻仅为1.47 m?·cm~2,因此获得了高达1966 MW·cm~(-2)的品质因数(FOM=BV~2/R_(on,sp)).相比于常规的AlGaN/GaN HEMT,基于新型p-GaN埋岛结构的HEMT器件在保持较低特征导通电阻的同时具有更高的击穿电压,这使得该结构在高功率电力电子器件领域具有很好的应用前景.     

Analysis of the modulation mechanisms of the electric field and breakdown performance in AlGaN/GaN HEMT with a T-shaped field-plate

A novel Al Ga N/Ga N high electron mobility transistor(HEMT) with a source-connected T-shaped field-plate(ST-FP HEMT) is proposed for the first time in this paper. The source-connected T-shaped field-plate(ST-FP) is composed of a source-connected field-plate(S-FP) and a trench metal. The physical intrinsic mechanisms of the ST-FP to improve the breakdown voltage and the FP efficiency and to modulate the distributions of channel electric field and potential are studied in detail by means of two-dimensional numerical simulations with Silvaco-ATLAS. A comparison to the HEMT and the HEMT with an S-FP(S-FP HEMT) shows that the ST-FP HEMT could achieve a broader and more uniform channel electric field distribution with the help of a trench metal, which could increase the breakdown voltage and the FP efficiency remarkably. In addition, the relationship between the structure of the ST-FP, the channel electric field, the breakdown voltage as well as the FP efficiency in ST-FP HEMT is analyzed. These results could open up a new effective method to fabricate high voltage power devices for the power electronic applications.     

Electrical and dielectric characterization of Au/ZnO/n-Si device depending frequency and voltage

Au/Zn O/n-type Si device is obtained using atomic layer deposition(ALD) for Zn O layer, and some main electrical parameters are investigated, such as surface/interface state(Nss), barrier height(Φb), series resistance(Rs), donor concentration(Nd), and dielectric characterization depending on frequency or voltage. These parameters are acquired by use of impedance spectroscopy measurements at frequencies ranging from 10 k Hz to 1 MHz and the direct current(DC) bias voltages in a range from-2 V to +2 V at room temperature are used. The main electrical parameters and dielectric parameters,such as dielectric constant(ε"), dielectric loss(ε"), loss tangent(tan δ), the real and imaginary parts of electric modulus(M and M), and alternating current(AC) electrical conductivity(σ) are affected by changing voltage and frequency. The characterizations show that some main electrical parameters usually decrease with increasing frequency because charge carriers at surface states have not enough time to fallow an external AC signal at high frequencies, and all dielectric parameters strongly depend on the voltage and frequency especially in the depletion and accumulation regions. Consequently, it can be concluded that interfacial polarization and interface charges can easily follow AC signal at low frequencies.