Synthesis, characterization of the pentacene and fabrication of pentacene field-effect transistors

A comprehensive understanding of the organic semiconductor material pentacene is meaningful for organic fieldeffect transistors （OFETs）. Thin films of pentacene are the most mobile molecular films known to date. This paper reported that the pentacene sample was successfully synthesized. The purity of pentacene is up to 95%. The results of a joint experimental investigation based on a combination of infrared absorption spectra, mass spectra （MS）, element analysis, x-ray diffraction （XRD） and atom force microscopy （AFM）. The authors fabricated OFET with the synthesized pentacene. Its field effect mobility is about 1.23 cm^2/（V·s） and on-off ratio is above 10^6.     

Modeling of a triple reduced surface field silicon-on-insulator lateral double-diffused metal–oxide–semiconductor field-effect transistor with low on-state resistance

An analytical model for a novel triple reduced surface field(RESURF) silicon-on-insulator(SOI) lateral doublediffused metal–oxide–semiconductor(LDMOS) field effect transistor with n-type top(N-top) layer, which can obtain a low on-state resistance, is proposed in this paper. The analytical model for surface potential and electric field distributions of the novel triple RESURF SOI LDMOS is presented by solving the two-dimensional(2D) Poisson's equation, which can also be applied to single, double and conventional triple RESURF SOI structures. The breakdown voltage(BV) is formulized to quantify the breakdown characteristic. Besides, the optimal integrated charge of N-top layer(Q_(ntop)) is derived, which can give guidance for doping the N-top layer. All the analytical results are well verified by numerical simulation results,showing the validity of the presented model. Hence, the proposed model can be a good tool for the device designers to provide accurate first-order design schemes and physical insights into the high voltage triple RESURF SOI device with N-top layer.     

Gate-modulated generation–recombination current in n-type metal–oxide–semiconductor field-effect transistor

Gate-modulated generation–recombination（GMGR） current IGMGRinduced by the interface traps in an n-type metal–oxide–semiconductor field-effect transistor（n MOSFET） is investigated. The generation current is found to expand rightwards with increasing the reversed drain PN junction bias, and the recombination current is enhanced as the forward drain bias increases. The variations of IGMGRcurves are ascribed to the changes of the electron density and hole density at the interface, NSand PS, under the different drain bias voltages. Based on an analysis of the physical mechanism, the IGMGR model is set up by introducing two coefficients（m and t）. The coefficients m and t can modulate the curves widths and peak values. The simulated results under reverse mode and forward mode are obviously in agreement with the experimental results. This proves that this model can be applicable for generation current and recombination current and that the theory behind the model is reasonable. The details of the relevant mechanism are given in the paper.     

Fabrication and characterization of bismuth oxide–holmia nanofibers and nanoceramics

In this article, a novel and simple method to produce both boron doped and undoped holmia stabilized bismuth oxide nanoceramic materials has been put forward. Boron doped and undoped poly (vinyl alcohol)/bismuth–holmia acetate nanofibers were produced using the electrospinning technique and were calcined at 850 °C afterward in order to obtain nanopowder. The characteristics of the nanofibers were investigated with FT-IR, XRD, and SEM. XRD analyses showed that boron undoped holmia stabilized bismuth oxide nanopowders have the face-centered cubic structure (δ-phase), and that the incorporation of boron atoms into the composite prevents the nucleus formation and turns the structure into a more amorphous glassy form. The SEM micrographs of the fibers showed that the addition of boron results in the formation of cross-linked bright-surfaced fibers. The average fiber diameters for electrospun boron doped and undoped PVA/Bi–Ho acetate nanofibers were calculated using the ImageJ software as 102 nm and 171 nm, respectively.     

Fabricating high performance n-channel lateral double diffused metal–oxide–semiconductor transistors utilizing the shallow trench isolation as a salicide blocking mask of the drift region

In this paper, the improved characteristics of 10 V tolerant high-voltage n-channel lateral double diffused metal–oxide–semiconductor (LDMOS) devices, using a pure 0.25 μm standard low-voltage complementary metal–oxide–semiconductor (CMOS) logic process with dual gate oxide, are described. The fabricated transistors showed about 30% better current driving characteristics and about 40% higher drain operating voltage than previous reports of these kinds of devices. The transistors maintained a breakdown voltage, BV_DSS, over 14 V. These devices also showed good sub-threshold characteristics. This paper describes the cost-effective and high performance n-channel high-voltage LDMOS using a pure low-voltage standard CMOS logic process.     

Fabrication and characterization of 4H—SiC bipolar junction transistor with double base epilayer

In this paper we report on a novel structure of a 4H-SiC bipolar junction transistor with a double base epilayer that is continuously grown.The measured dc common-emitter current gain is 16.8 at IC = 28.6 mA(J C = 183.4 A/cm2),and it increases with the collector current density increasing.The specific on-state resistance(Rsp-on) is32.3mΩ·cm 2 and the open-base breakdown voltage reaches 410 V.The emitter N-type specific contact resistance and N + emitter layer sheet resistance are 1.7×10-3 Ω·cm2 and 150 /,respectively.     

Investigation of trap states in Al_2O_3 InAlN/GaN metal–oxide–semiconductor high-electron-mobility transistors

In this paper the trapping effects in Al2O3/In0.17Al0.83N/Ga N MOS-HEMT(here, HEMT stands for high electron mobility transistor) are investigated by frequency-dependent capacitance and conductance analysis. The trap states are found at both the Al2O3/In Al N and In Al N/Ga N interface. Trap states in In Al N/Ga N heterostructure are determined to have mixed de-trapping mechanisms, emission, and tunneling. Part of the electrons captured in the trap states are likely to tunnel into the two-dimensional electron gas(2DEG) channel under serious band bending and stronger electric field peak caused by high Al content in the In Al N barrier, which explains the opposite voltage dependence of time constant and relation between the time constant and energy of the trap states.     

Dual-gate lateral double-diffused metal—oxide semiconductor with ultra-low specific on-resistance

A new high voltage trench lateral double-diffused metal-oxide semiconductor (LDMOS) with ultra-low specific onresistance (R on,sp ) is proposed. The structure features a dual gate (DG LDMOS): a planar gate and a trench gate inset in the oxide trench. Firstly, the dual gate can provide a dual conduction channel and reduce R on,sp dramatically. Secondly, the oxide trench in the drift region modulates the electric field distribution and reduces the cell pitch but still can maintain comparable breakdown voltage (BV). Simulation results show that the cell pitch of the DG LDMOS can be reduced by 50% in comparison with that of conventional LDMOS at the equivalent BV; furthermore, R on,sp of the DG LDMOS can be reduced by 67% due to the smaller cell pitch and the dual gate.     

Improved performance of 4H-SiC metal-semiconductor field-effect transistors with step p-buffer layer

An improved 4H-SiC metal-semiconductor field-effect transistors (MESFETs) with step p-buffer layer is proposed, and the static and dynamic electrical performances are analysed in this paper. A step p-buffer layer has been applied not only to increase the channel current, but also to improve the transconductance. This is due to the fact that the variation in p-buffer layer depth leads to the decrease in parasitic series resistance resulting from the change in the active channel thickness and modulation in the electric field distribution inside the channel. Detailed numerical simulations demonstrate that the saturation drain current and the maximum theoretical output power density of the proposed structure are about 30% and 37% larger than those of the conventional structure. The cut-off frequency and the maximum oscillation frequency of the proposed MESFETs are 14.5 and 62 GHz, respectively, which are higher than that of the conventional structure. Therefore, the 4H-SiC MESFETs with step p-buffer layer have superior direct-current and radio-frequency performances compared to the similar devices based on the conventional structure.     

Evaluation of a gate-first process for AlGaN/GaN metal-oxide-semiconductor heterostructure field-effect transistors with low ohmic annealing temperature

In this paper, TiN/AlO_x gated Al Ga N/Ga N metal–oxide–semiconductor heterostructure field-effect transistors(MOSHFETs) were fabricated for gate-first process evaluation. By employing a low temperature ohmic process, ohmic contact can be obtained by annealing at 600℃ with the contact resistance approximately 1.6 ?·mm. The ohmic annealing process also acts as a post-deposition annealing on the oxide film, resulting in good device performance. Those results demonstrated that the TiN/AlO_x gated MOS-HFETs with low temperature ohmic process can be applied for self-aligned gate Al Ga N/Ga N MOS-HFETs.     

Thickness dependence of surface morphology and charge carrier mobility in organic field-effect transistors

With the aim of understanding the relationships between organic small molecule field-effect transistors (FETs) and organic conjugated polymer FETs, we investigate the thickness dependence of surface morphology and charge carrier mobility in pentacene and regioregular poly (3-hexylthiophene) (RR-P3HT) field-effect transistors. On the basis of the results of surface morphologies and electrical properties, we presume that the charge carrier mobility is largely related to the morphology of the organic active layer. We observe that the change trends of the surface morphologies (average size and average roughness) of pentacene and RR-P3HT thin films are mutually opposite, as the thickness of the organic layer increases. Further, we demonstrate that the change trends of the field-effect mobilities of pentacene and RR-P3HT FETs are also opposite to each other, as the thickness of the organic layer increases within its limit.     

基于栅绝缘层表面修饰的有机场效应晶体管迁移率的研究进展

栅绝缘层的表面性质对有机场效应晶体管（OFETs）的半导体薄膜的形貌、晶粒生长的有序性和载流子的传输有着重大的影响．研究表明,通过改进栅绝缘层的表面性质,可以有效提高有机场效应晶体管的迁移率．本文综述了OFETs绝缘层表面的粗糙度和表面能对OFETs迁移率的影响,重点探讨了栅绝缘层表面修饰常用的方法,即自组装单层（SAMs）修饰和聚合物修饰与迁移率改进之间的研究进展．最后,展望了该研究方向未来可能的发展趋势．     

具有P型覆盖层新型超级结横向双扩散功率器件

为了设计功率集成电路所需要的低功耗横向双扩散金属氧化物半导体器件(lateral double-diffused MOSFET), 在已有的N型缓冲层超级结LDMOS(N-buffered-SJ-LDMOS)结构基础上, 提出了一种具有P型覆盖层新型超级结LDMOS结构(P-covered-SJ-LDMOS). 这种结构不但能够消除传统的N沟道SJ-LDMOS由于P型衬底产生的衬底辅助耗尽问题, 使得超级结层的N区和P区的电荷完全补偿, 而且还能利用覆盖层的电荷补偿作用, 提高N型缓冲层浓度, 从而降低了器件的比导通电阻. 利用三维仿真软件ISE分析表明, 在漂移区长度均为10 μm的情况下, P-covered-SJ-LDMOS的比导通电阻较一般SJ-LDMOS结构降低了59%左右, 较文献提出的N型缓冲层 SJ-LDMOS(N-buffered-SJ-LDMOS)结构降低了43%左右.     

Effects of quantum coupling on the performance of metal-oxide-semiconductor field transistors

Based on the analysis of the three-dimensional Schrödinger equation, the effects of quantum coupling between the transverse and the longitudinal components of channel electron motion on the performance of ballistic MOSFETs have been theoretically investigated by self-consistently solving the coupled Schrödinger-Poisson equations with the finite-difference method. The results show that the quantum coupling between the transverse and the longitudinal components of the electron motion can largely affect device performance. It suggests that the quantum coupling effect should be considered for the performance of a ballistic MOSFET due to the high injection velocity of the channel electron.     

Effect of NO annealing on charge traps in oxide insulator and transition layer for 4H-SiC metal–oxide–semiconductor devices

The effect of nitric oxide(NO) annealing on charge traps in the oxide insulator and transition layer in n-type4H–Si C metal–oxide–semiconductor(MOS) devices has been investigated using the time-dependent bias stress(TDBS),capacitance–voltage(C–V),and secondary ion mass spectroscopy(SIMS).It is revealed that two main categories of charge traps,near interface oxide traps(Nniot) and oxide traps(Not),have different responses to the TDBS and C–V characteristics in NO-annealed and Ar-annealed samples.The Nniotare mainly responsible for the hysteresis occurring in the bidirectional C–V characteristics,which are very close to the semiconductor interface and can readily exchange charges with the inner semiconductor.However,Not is mainly responsible for the TDBS induced C–V shifts.Electrons tunneling into the Not are hardly released quickly when suffering TDBS,resulting in the problem of the threshold voltage stability.Compared with the Ar-annealed sample,Nniotcan be significantly suppressed by the NO annealing,but there is little improvement of Not.SIMS results demonstrate that the Nniotare distributed within the transition layer,which correlated with the existence of the excess silicon.During the NO annealing process,the excess Si atoms incorporate into nitrogen in the transition layer,allowing better relaxation of the interface strain and effectively reducing the width of the transition layer and the density of Nniot.     

Effects of concentration and annealing on the performance of regioregular poly（3-hexylthiophene） field-effect transistors

This paper investigates the effects of concentration on the crystalline structure, the morphology, and the charge carrier mobility of regioregular poly(3-hexylthiophene) (RR-P3HT) field-effect transistors (FETs). The RR-P3HT FETs with RR-P3HT as an active layer with different concentrations of RR-P3HT solution from 0.5~wt% to 2~wt% are prepared. The results indicate that the performance of RR-P3HT FETs improves drastically with the increase of RR-P3HT weight percentages in chloroform solution due to the formation of more microcrystalline lamellae and bigger nanoscale islands. It finds that the field-effect mobility of RR-P3HT FET with 2~wt% can reach 5.78× 10^-3~cm²/Vs which is higher by a factor of 13 than that with 0.5~wt%. Further, an appropriate thermal annealing is adopted to improve the performance of RR-P3HT FETs. The field-effect mobility of RR-P3HT FETs increases drastically to 0.09~cm²/Vs by thermal annealing at 150~℃, and the value of on/off current ratio can reach 10^4.     

GaSb p-channel metal-oxide-semiconductor field-effect transistor and its temperature dependent characteristics

GaSb p-channel metal-oxide-semiconductor field-effect transistors(MOSFETs)with an atomic layer deposited Al2O3gate dielectric and a self-aligned Si-implanted source/drain are experimentally demonstrated.Temperature dependent electrical characteristics are investigated.Different electrical behaviors are observed in two temperature regions,and the underlying mechanisms are discussed.It is found that the reverse-bias pn junction leakage of the drain/substrate is the main component of the off-state drain leakage current,which is generation-current dominated in the low temperature regions and is diffusion-current dominated in the high temperature regions.Methods to further reduce the off-state drain leakage current are given.