考虑量子化效应的MOSFET阈值电压解析模型

根据改进后的三角势阱场近似，并考虑量子化效应，提出了一种基于物理的阈值电压解析模型，给出了MOSFET的阈值电压解析表达式，并与经典理论和数值模拟结果进行了比较. 关键词： 量子效应 阈值电压 反型层 表面势     

亚100 nm应变Si/SiGe nMOSFET阈值电压二维解析模型

本文基于二维泊松方程,建立了适用于亚100 nm应变Si/SiGe nMOSFET的阈值电压理论模型.为了保证该模型的准确性,同时考虑了器件尺寸减小所导致的物理效应,如短沟道效应,量子化效应等.通过将模型的计算结果与二维器件模拟器ISE的仿真结果进行对比分析,证明了本文提出的模型的正确性.最后,还讨论了亚100 nm器件中常规工艺对阈值电压的影响.该模型为亚100 nm小尺寸应变Si器件的分析设计提供了一定的参考. 关键词： 亚100nm 应变Si/SiGe nMOSFET 二维表面势 阈值电压     

应变Si沟道nMOSFET阈值电压模型

在研究分析弛豫SiGe衬底上的应变Si 沟道nMOSFET纵向电势分布的基础上,建立了应变Si nMOSFET阈值电压模型,并利用该模型对不同的器件结构参数进行仿真,获得了阈值电压与SiGe层掺杂浓度和Ge组分的关系、阈值电压偏移量与SiGe层中Ge组分的关系、阈值电压与应变Si层掺杂浓度和厚度的关系. 分析结果表明：阈值电压随SiGe层中Ge组分的提高而降低,随着SiGe层的掺杂浓度的提高而增大;阈值电压随应变Si层的掺杂浓度的提高而增大,随应变Si层厚度增大而增大. 该模型为应变Si 器件阈值电压设计 关键词： 应变硅 阈值电压 电势分布 反型层     

高k栅介质GeOI金属氧化物半导体场效应管阈值电压和亚阈斜率模型及其器件结构设计

通过求解沟道与埋氧层的二维泊松方程,同时考虑垂直沟道与埋氧层方向的二阶效应,建立了高κ栅介质GeOI金属氧化物半导体场效应管(MOSFET)的阈值电压和亚阈斜率解析模型,研究了器件主要结构参数对器件阈值特性、亚阈特性、短沟道效应、漏极感应势垒降低效应及衬偏效应的影响,提出了优化器件性能的结构参数设计原则及取值范围,模拟结果与TCAD仿真结果符合较好,证实了模型的正确性与实用性。     

具有高阈值电压和大栅压摆幅的常关型槽栅AlGaN/GaN金属氧化物半导体高电子迁移率晶体管

介绍了一种具有高阈值电压和大栅压摆幅的常关型槽栅AlGaN/GaN金属氧化物半导体高电子迁移率晶体管。采用原子层淀积(ALD)方法实现Al₂O₃栅介质的沉积。槽栅常关型AlGaN/GaN MOS-HEMT的栅长(L_g)为2 μm,栅宽(W_g)为0.9 mm(0.45 mm×2),栅极和源极(L_gs)之间的距离为5 μm,栅极和漏极(L_gd)之间的距离为10 μm。在栅压为－20 V时,槽栅常关型AlGaN/GaN MOS-HEMT的栅漏电仅为0.65 nA。在栅压为+12 V时,槽栅常关型AlGaN/GaN MOS-HEMT的栅漏电为225 nA。器件的栅压摆幅为－20~+12 V。在栅压V_gs=+10 V时,槽栅常关型AlGaN/GaN MOS-HEMT电流和饱和电流密度分别达到了98 mA和108 mA/mm (W_g=0.9 mm), 特征导通电阻为4 mΩ·cm²。槽栅常关型AlGaN/GaN MOS-HEMT的阈值电压为+4.6 V,开启与关断电流比达到了5×10⁸。当V_ds=7 V时,器件的峰值跨导为42 mS/mm (W_g=0.9 mm,V_gs=+10 V)。在V_gs=0 V时,栅漏间距为10 μm的槽栅常关型AlGaN/GaN MOS-HEMT的关断击穿电压为450 V,关断泄露电流为0.025 mA/mm。     

单Halo全耗尽应变Si 绝缘硅金属氧化物半导体场效应管的阈值电压解析模型

为了改善金属氧化物半导体场效应管(MOSFET) 的短沟道效应(SCE)、 漏致势垒降低(DIBL) 效应, 提高电流的驱动能力, 提出了单Halo 全耗尽应变硅绝缘体 (SOI) MOSFET 结构, 该结构结合了应变Si, 峰值掺杂Halo结构, SOI 三者的优点. 通过求解二维泊松方程, 建立了全耗尽器件表面势和阈值电压的解析模型. 模型中分析了弛豫层中的Ge组分对表面势、表面场强和阈值电压的影响, 不同漏电压对表面势的影响, Halo 掺杂对阈值电压和DIBL的影响.结果表明, 该新结构能够抑制SCE和DIBL效应, 提高载流子的输运效率. 关键词： 应变Si 阈值电压 短沟道效应 漏致势垒降低     

多晶SiGe栅量子阱pMOSFET阈值电压模型

本文基于多晶SiGe栅量子阱SiGe pMOSFET器件物理,考虑沟道反型时自由载流子对器件纵向电势的影响,通过求解泊松方程,建立了p+多晶SiGe栅量子阱沟道pMOS阈值电压和表面寄生沟道开启电压模型.应用MATLAB对该器件模型进行了数值分析,讨论了多晶Si_1-yGe_y栅Ge组分、Si_1-xGe_x量子阱沟道Ge组分、栅氧化层厚度、Si帽层厚度、沟道区掺杂浓度和 关键词： 多晶SiGe栅 寄生沟道 量子阱沟道 阈值电压     

应变绝缘层上硅锗p型金属氧化物场效应晶体管的阈值电压解析模型

分析研究了应变绝缘层上硅锗p型金属氧化物场效应晶体管(SGOI pMOSFET)的阈值电压模型,修正了应变作用下SGOI pMOSFET的能带模型,并提取了主要的物理参量.这些典型的参量包括禁带宽度、电子亲和能、内建势等.给出了应变硅SGOI pMOSFET内部电势分布的二维泊松方程,通过边界条件求解方程,得出了准确的阈值电压模型,并且验证了该模型的正确性.     

应变SiGe SOI量子阱沟道PMOSFET阈值电压模型研究

在绝缘层附着硅(SOI)结构的Si膜上生长SiGe合金制作具有SiGe量子阱沟道的SOI p型金属氧化物半导体场效应晶体管(PMOSFET)，该器件不仅具有SOI结构的优点，而且因量子阱中载流子迁移率高，所以进一步提高了器件的性能.在分析常规的Si SOI MOSFET基础上，建立了应变SiGe SOI 量子阱沟道PMOSFET的阈值电压模型和电流-电压(I-V)特性模型，利用Matlab对该结构器件的I-V特性、跨导及漏导特性进行了模拟分析，且与常规结构的器件作了对比.模拟结果表明，应变SiGe SOI量子阱沟道PMOSFET的性能均比常规结构的器件有大幅度提高. 关键词： 应变SiGe SOI MOSFET 阈值电压 模型     

考虑量子效应的短沟道MOSFET二维阈值电压模型

通过数值方法求解泊松方程和薛定谔方程的自洽解，提出了考虑量子效应时不同于经典理论的阈值条件，并得出了精确的一维阈值电压模型，模拟结果与实验十分符合.在此基础上，基于准二维泊松方程，通过考虑短沟道效应和量子效应，建立了较为精确的适合于小尺寸MOSFET的量子修正阈值电压模型,模型同样适用于(超)深亚微米高k栅介质MOSFET电特性的模拟和结构参数的设计. 关键词： 阈值电压 量子效应 短沟道效应 高k栅介质     

A new structure and its analytical model for the vertical interface electric field of a partial-SOI high voltage device

A new partial-SOI (PSOI) high voltage device structure called a CI PSOI (charge island PSOI) is proposed for the first time in this paper. The device is characterized by a charge island layer on the interface of the top silicon layer and the dielectric buried layer in which a series of equidistant high concentration n⁺-regions is inserted. Inversion holes resulting from the vertical electric field are located in the spacing between two neighbouring n⁺-regions on the interface by the force with ionized donors in the undepleted n⁺-regions, and therefore effectively enhance the electric field of the dielectric buried layer (E_I) and increase the breakdown voltage (BV), thereby alleviating the self-heating effect (SHE) by the silicon window under the source. An analytical model of the vertical interface electric field for the CI PSOI is presented and the analytical results are in good agreement with the 2D simulation results. The BV and E_I of the CI PSOI LDMOS increase to 631~V and 584~V/μ m from 246~V and 85.8~V/μ m for the conventional PSOI with a lower SHE, respectively. The effects of the structure parameters on the device characteristics are analysed for the proposed device in detail.     

具有纵向漏极场板的低导通电阻绝缘体上硅横向双扩散金属氧化物半导体器件新结构

为降低绝缘体上硅(SOI)横向双扩散金属氧化物半导体(LDMOS)器件的导通电阻,同时提高器件击穿电压,提出了一种具有纵向漏极场板的低导通电阻槽栅槽漏SOI-LDMOS器件新结构.该结构特征为采用了槽栅槽漏结构,在纵向上扩展了电流传导区域,在横向上缩短了电流传导路径,降低了器件导通电阻;漏端采用了纵向漏极场板,该场板对漏端下方的电场进行了调制,从而减弱了漏极末端的高电场,提高了器件的击穿电压.利用二维数值仿真软件MEDICI对新结构与具有相同器件尺寸的传统SOI结构、槽栅SOI结构、槽栅槽漏SOI结构进行了比较.结果表明:在保证各自最高优值的条件下,与这三种结构相比,新结构的比导通电阻分别降低了53%,23%和提高了87%,击穿电压则分别提高了4%、降低了9%、提高了45%.比较四种结构的优值,具有纵向漏极场板的槽栅槽漏SOI结构优值最高,这表明在四种结构中新结构保持了较低导通电阻,同时又具有较高的击穿电压.     

频率对半导体器件热击穿影响的理论模型

针对半导体器件中的热击穿,通过分析已有的理论模型,把频率对器件热区热产生和热传导的影响引入理论模型.利用格林函数求解热传输方程,同时对余误差函数进行近似处理,求解得到热区温度以及器件烧毁功率与频率和脉冲宽度的表达式.通过数值分析,求解得到不同频率下器件烧毁功率随脉冲宽度的变化规律以及不同脉冲宽度下器件烧毁功率随频率的变化规律,同时给出了频率对器件烧毁功率影响的物理解释.     

应变Si全耗尽SOI MOSFET二维亚阈电流模型

本文通过求解二维泊松方程,为应变Si 全耗SOI MOSFET建立了全耗尽条件下表面势模型,利用传统的漂移-扩散理论.在表面势模型的基础上,得到了应变Si 全耗SOI MOSFET的亚阈电流模型,并通过与二维器件数值模拟工具ISE的结果做比较,证明了所建立的模型的正确性.根据所建立的模型,分析了亚阈电流跟应变Si应变度的大小,应变Si膜的厚度和掺杂浓度的关系,为应变Si 全耗SOI MOSFET物理参数设计提供了重要参考. 关键词： 应变硅 FD-SOI MOSFET 表面势 亚阈电流     

A novel thin drift region device with field limiting rings in substrate

A novel thin drift region device with heavily doped N⁺ rings embedded in the substrate is reported, which is called the field limiting rings in substrate lateral double-diffused MOS transistor (SFLR LDMOS). In the SFLR LDMOS, the peak of the electric field at the main junction is reduced due to the transfer of the voltage from the main junction to other field limiting ring junctions, so the vertical electric field is improved significantly. A model of the breakdown voltage is developed, from which optimal spacing is obtained. The numerical results indicate that the breakdown voltage of the device proposed is increased by 76% in comparison to that of the conventional LDMOS.     

Comparative investigation of the resistance and ability to trigger high voltage discharge for single and multiple femtosecond filaments in air

A comparative investigation of the resistance and ability to trigger high voltage(HV) discharge for a single filament(SF) and multiple filaments(MFs) has been carried out.The experimental results show that the trend of the breakdown threshold of the SF exactly follows that of its resistance,but this is not the case for the MF.The MF’s resistance is much smaller than the SF’s.However,the MF shows a slightly higher HV breakdown threshold than the SF.The underlying physics is that the measured resistance of the MF is collectively contributed by every filament in the MF while the HV breakdown threshold is determined by only one single discharging path.     

Analysis of the breakdown mechanism for an ultra high voltage high-side thin layer silicon-on-insulator p-channel low-density metal-oxide semiconductor

This paper discusses the breakdown mechanism and proposes a new simulation and test method of breakdown voltage(BV) for an ultra-high-voltage(UHV) high-side thin layer silicon-on-insulator(SOI) p-channel lateral double-diffused metal-oxide semiconductor(LDMOS).Compared with the conventional simulation method,the new one is more accordant with the actual conditions of a device that can be used in the high voltage circuit.The BV of the SOI p-channel LDMOS can be properly represented and the effect of reduced bulk field can be revealed by employing the new simulation method.Simulation results show that the off-state(on-state) BV of the SOI p-channel LDMOS can reach 741(620) V in the 3-μm-thick buried oxide layer,50-μm-length drift region,and at 400 V back-gate voltage,enabling the device to be used in a 400 V UHV integrated circuit.     

One-dimensional breakdown voltage model of SOI RESURF lateral power device based on lateral linearly graded approximation

A novel one-dimensional(1D) analytical model is proposed for quantifying the breakdown voltage of a reduced surface field(RESURF) lateral power device fabricated on silicon on an insulator(SOI) substrate.We assume that the charges in the depletion region contribute to the lateral PN junctions along the diagonal of the area shared by the lateral and vertical depletion regions.Based on the assumption,the lateral PN junction behaves as a linearly graded junction,thus resulting in a reduced surface electric field and high breakdown voltage.Using the proposed model,the breakdown voltage as a function of device parameters is investigated and compared with the numerical simulation by the TCAD tools.The analytical results are shown to be in fair agreement with the numerical results.Finally,a new RESURF criterion is derived which offers a useful scheme to optimize the structure parameters.This simple 1D model provides a clear physical insight into the RESURF effect and a new explanation on the improvement in breakdown voltage in an SOI RESURF device.