绝缘栅双极晶体管串联应用中暂态均压特性

采用金属球隙放电的方式模拟了负载短路时的暂态过程。通过引线自感公式计算法和电路状态分析法估算脉冲放电回路的杂散电感数值,并采用传统RCD均压网络的绝缘栅双极晶体管串联链进行各元件参数差异下的蒙特卡罗仿真分析,发现影响串联链暂态均压特性的关键元件是栅极稳压二极管和动态均压电容。因此为了提高这类拓扑结构的串联链的可靠性,在筛选元件时要尤其注意栅极稳压二极管的限幅保持一致。     

绝缘栅双极晶体管串联应用中暂态均压特性

采用金属球隙放电的方式模拟了负载短路时的暂态过程。通过引线自感公式计算法和电路状态分析法估算脉冲放电回路的杂散电感数值,并采用传统RCD均压网络的绝缘栅双极晶体管串联链进行各元件参数差异下的蒙特卡罗仿真分析,发现影响串联链暂态均压特性的关键元件是栅极稳压二极管和动态均压电容。因此为了提高这类拓扑结构的串联链的可靠性,在筛选元件时要尤其注意栅极稳压二极管的限幅保持一致。     

10kV绝缘栅双极型晶体管固体开关的研制

 采用8只IXLF19N250A绝缘栅双极型晶体管串联研制成功了10kV固体开关。试验表明：该固体开关最高输出电压为14kV，最高输出脉冲电流为20A、输出脉冲宽度可在2~112μs之间以1μs步长变化，脉冲重复频率范围为1Hz~4kHz，短时间可以工作到8.6kHz。     

10kV绝缘栅双极型晶体管固体开关的研制

采用8只IXLF19N250A绝缘栅双极型晶体管串联研制成功了10kV固体开关。试验表明:该固体开关最高输出电压为14kV，最高输出脉冲电流为20A、输出脉冲宽度可在2~112μs之间以1μs步长变化，脉冲重复频率范围为1Hz~4kHz，短时间可以工作到8.6kHz。     

绝缘栅双极晶体管串联关键技术

为实现绝缘栅双极晶体管（IGBT）的多级串联,以电阻/电容/二极管（RCD）缓冲电路为动态均压电路,通过数学分析及PSpice仿真验证,建立了RCD缓冲电路参数选择模型;设计了基于数字信号处理器（DSP）控制、光纤隔离传输,以M57962L为IGBT驱动器的驱动电路及故障反馈电路,能驱动32只串联IGBT并对其进行过流和短路保护,32只IGBT的最大导通时间不超过90 ns,短路保护响应时间约为6 s;设计了8路独立输出的50 kV隔离的高压隔离电源,实现IGBT串联电路各部分的供电及电隔离。基于以上IGBT串联方法,实现了32只1200 V IGBT的串联,串联电路可稳定工作在20 kV电压下。     

绝缘栅双极晶体管串联关键技术

为实现绝缘栅双极晶体管（IGBT）的多级串联,以电阻/电容/二极管（RCD）缓冲电路为动态均压电路,通过数学分析及PSpice仿真验证,建立了RCD缓冲电路参数选择模型;设计了基于数字信号处理器（DSP）控制、光纤隔离传输,以M57962L为IGBT驱动器的驱动电路及故障反馈电路,能驱动32只串联IGBT并对其进行过流和短路保护,32只IGBT的最大导通时间不超过90 ns,短路保护响应时间约为6 s;设计了8路独立输出的50 kV隔离的高压隔离电源,实现IGBT串联电路各部分的供电及电隔离。基于以上IGBT串联方法,实现了32只1200 V IGBT的串联,串联电路可稳定工作在20 kV电压下。     

高频电容器充电电源绝缘栅双极晶体管吸收电路

高频化是提升电源功率密度的有效方法。为了保护高频电容器充电电源中的开关器件,以串联谐振式电容器充电电源为基础,研究了绝缘栅双极晶体管(IGBT)尖峰电压的产生机理及影响因素。介绍了几种抑制尖峰电压的方法,着重分析了IGBT吸收电路的基本原理,并进行了参数设计。结合仿真软件,对吸收电路的参数进行了优化,将仿真结果和40 kW,50 kHz电容器充电电源样机的实验结果进行对比,验证了提出方案的可行性。     

高频电容器充电电源绝缘栅双极晶体管吸收电路

 高频化是提升电源功率密度的有效方法。为了保护高频电容器充电电源中的开关器件,以串联谐振式电容器充电电源为基础,研究了绝缘栅双极晶体管(IGBT)尖峰电压的产生机理及影响因素。介绍了几种抑制尖峰电压的方法,着重分析了IGBT吸收电路的基本原理,并进行了参数设计。结合仿真软件,对吸收电路的参数进行了优化,将仿真结果和40 kW,50 kHz电容器充电电源样机的实验结果进行对比,验证了提出方案的可行性。     

InP/In0.53Ga0.47As/InP双异质结双极型晶体管的仿真与分析

运用Silvaco-TCAD软件构建了InP/In_(0.53)Ga_(0.47)As/InP双异质结双极型晶体管模型,研究了掺杂浓度、厚度以及温度对器件特性的影响.结果表明:双异质结双极型晶体管DHBT的开启电压能达到约0.4V,当浓度达到4×10^(19) cm^(-3)的时候,电流增益可以达到一个最佳状态,其峰值能达到约125左右,且浓度对截止频率以及最高振荡频率没有太大的影响;当增大基区厚度时,电流增益会减小,改变厚度能够使DHBT输出特性得以提升,并且提高基区电流的注入;双异质结双极型晶体管具有很好的温度稳定性.     

基于波形测试的异质结双极型晶体管器件负载失配影响分析

大功率电磁脉冲冲击下,射频集成微系统内部容易产生负载失配问题,严重者可能导致系统失效甚至损毁。采用实时的波形测试方法,对射频器件的负载失配进而导致器件损毁的机理进行了分析。该方法以矢量网络分析仪作为主要测试仪器,结合回波信号注入和相位参考模块获得待测器件实时电压电流波形,进而分析其负载失配影响机制。采用有源负载牵引技术模拟大功率耦合电磁脉冲注入,进行了电压驻波比39∶1的失配测试,大幅提升了测试范围。创新性地采用了谐波信号源注入模拟杂散谐波电磁干扰,评估器件的谐波阻抗失配特性。通过实际异质结双极型晶体管（HBT）器件测试的结果表明,基波的失配会造成负载端电压过大,增加器件的易损性;基波和谐波频率的干扰分量组合使得输出电压瞬态峰值升高,造成器件的损毁。在进行电磁安全防护时,应同时考虑基波和谐波频率的防护。     

A high voltage silicon-on-insulator lateral insulated gate bipolar transistor with a reduced cell-pitch

A high voltage( 600 V) integrable silicon-on-insulator(SOI) trench-type lateral insulated gate bipolar transistor(LIGBT) with a reduced cell-pitch is proposed.The LIGBT features multiple trenches(MTs):two oxide trenches in the drift region and a trench gate extended to the buried oxide(BOX).Firstly,the oxide trenches enhance electric field strength because of the lower permittivity of oxide than that of Si.Secondly,oxide trenches bring in multi-directional depletion,leading to a reshaped electric field distribution and an enhanced reduced-surface electric-field(RESURF) effect.Both increase the breakdown voltage(BV).Thirdly,oxide trenches fold the drift region around the oxide trenches,leading to a reduced cell-pitch.Finally,the oxide trenches enhance the conductivity modulation,resulting in a high electron/hole concentration in the drift region as well as a low forward voltage drop(Von).The oxide trenches cause a low anode-cathode capacitance,which increases the switching speed and reduces the turn-off energy loss(Eoff).The MT SOI LIGBT exhibits a BV of 603 V at a small cell-pitch of 24 μm,a Von of 1.03 V at 100 A/cm-2,a turn-off time of 250 ns and Eoff of 4.1×10?3 mJ.The trench gate extended to BOX synchronously acts as dielectric isolation between high voltage LIGBT and low voltage circuits,simplifying the fabrication processes.     

A dual-gate and dielectric-inserted lateral trench insulated gate bipolar transistor on a silicon-on-insulator substrate

In this paper, a novel dual-gate and dielectric-inserted lateral trench insulated gate bipolar transistor (DGDI LTIGBT) structure, which features a double extended trench gate and a dielectric inserted in the drift region, is proposed and discussed. The device can not only decrease the specific on-resistance Ron,sp , but also simultaneously improve the temperature performance. Simulation results show that the proposed LTIGBT achieves an ultra-low on-state voltage drop of 1.31 V at 700 A·cm-2 with a small half-cell pitch of 10.5 μm, a specific on-resistance R on,sp of 187 mΩ·mm2,and a high breakdown voltage of 250 V. The on-state voltage drop of the DGDI LTIGBT is 18% less than that of the DI LTIGBT and 30.3% less than that of the conventional LTIGBT. The proposed LTIGBT exhibits a good positive temperature coefficient for safety paralleling to handling larger currents and enhances the short-circuit capability while maintaining a low self-heating effect. Furthermore, it also shows a better tradeoff between the specific on-resistance and the turnoff loss, although it has a longer turnoff delay time.     

一种考虑IGBT基区载流子注入条件的物理模型

提出了一种考虑绝缘栅极双极晶体管(insulated gate bipolar transistor,IGBT) 基区载流子不同注入条件的物理模型. 在小注入和大注入情况下,分别建立描述IGBT基区载流子运动的输运方程(ambipolar transport equation,ATE),并确定边界条件. 采用傅里叶级数法求解载流子输运方程,并将计算结果分别与IGBT手册提供的实验数据和Hefner模型计算结果相比较,验证了本文提出物理模型的正确性. 关键词： 绝缘栅极双极晶体管 物理模型 注入条件 双极输运方程     

具有poly-Si$lt;sub$gt;1-$lt;i$gt;x$lt;/i$gt;$lt;/sub$gt;Ge$lt;sub$gt;$lt;i$gt;x$lt;/i$gt;$lt;/sub$gt;栅的应变SiGep型金属氧化物半导体场效应晶体管阈值电压漂移模型研究

针对具有poly-Si_1-xGe_x栅的应变SiGe p型金属氧化物半导体场效应晶体管(PMOSFET), 研究了其垂直电势与电场分布, 建立了考虑栅耗尽的poly-Si_1-xGe_x栅情况下该器件的等效栅氧化层厚度模型, 并利用该模型分析了poly-Si_1-xGe_x栅及应变SiGe层中Ge组分对等效氧化层厚度的影响. 研究了应变SiGe PMOSFET热载流子产生的机理及其对器件性能的影响, 以及引起应变SiGe PMOSFET阈值电压漂移的机理, 并建立了该器件阈值电压漂移模型, 揭示了器件阈值电压漂移随电应力施加时间、栅极电压、poly-Si_1-xGe_x栅及应变SiGe层中Ge组分的变化关系. 并在此基础上进行了实验验证, 在电应力施加10000 s时, 阈值电压漂移0.032 V, 与模拟结果基本一致, 为应变SiGe PMOSFET及相关电路的设计与制造提供了重要的理论与实践基础. 关键词： 应变SiGep型金属氧化物半导体场效应晶体管 1-xGe_x栅')" href="#">poly-Si_1-xGe_x栅 热载流子 阈值电压     

Characteristics of pentacene organic thin film transistor with top gate and bottom contact

High performance pentacene organic thin film transistors (OTFT) were designed and fabricated using SiO₂ deposited by electron beam evaporation as gate dielectric material. Pentacene thin films were prepared on glass substrate with S--D electrode pattern made from ITO by means of thermal evaporation through self-organized process. The threshold voltage V_TH was --2.75± 0.1V in 0---50V range, and that subthreshold slopes were 0.42± 0.05V/dec. The field-effect mobility (μ_EF) of OTFT device increased with the increase of V_DS, but the μ_EF of OTFT device increased and then decreased with increased V_GS when V_DS was kept constant. When V_DS was --50V, on/off current ratio was 0.48× 10⁵ and subthreshold slope was 0.44V/dec. The μ_EF was 1.10cm²/(V.s), threshold voltage was --2.71V for the OTFT device.     

Ultralow turnoff loss dual-gate SOI LIGBT with trench gate barrier and carrier stored layer

A novel ultralow turnoff loss dual-gate silicon-on-insulator(SOI) lateral insulated gate bipolar transistor(LIGBT) is proposed. The proposed SOI LIGBT features an extra trench gate inserted between the p-well and n-drift, and an n-type carrier stored(CS) layer beneath the p-well. In the on-state, the extra trench gate acts as a barrier, which increases the carrier density at the cathode side of n-drift region, resulting in a decrease of the on-state voltage drop(Von). In the off-state, due to the uniform carrier distribution and the assisted depletion effect induced by the extra trench gate, large number of carriers can be removed at the initial turnoff process, contributing to a low turnoff loss(Eoff). Moreover, owing to the dual-gate field plates and CS layer, the carrier density beneath the p-well can greatly increase, which further improves the tradeoff between Eoffand Von. Simulation results show that Eoff of the proposed SOI LIGBT can decrease by 77% compared with the conventional trench gate SOI LIGBT at the same Von of 1.1 V.     

Effect of gate length on breakdown voltage in AlGaN/GaN high-electron-mobility transistor

The effects of gate length L_G on breakdown voltage VBRare investigated in AlGaN/GaN high-electron-mobility transistors(HEMTs) with L_G= 1 μm~20 μm. With the increase of L_G, VBRis first increased, and then saturated at LG= 3 μm. For the HEMT with L_G= 1 μm, breakdown voltage VBRis 117 V, and it can be enhanced to 148 V for the HEMT with L-_G= 3 μm. The gate length of 3 μm can alleviate the buffer-leakage-induced impact ionization compared with the gate length of 1 μm, and the suppression of the impact ionization is the reason for improving the breakdown voltage.A similar suppression of the impact ionization exists in the HEMTs with LG 3 μm. As a result, there is no obvious difference in breakdown voltage among the HEMTs with LG= 3 μm~20 μm, and their breakdown voltages are in a range of 140 V–156 V.