具有L型源极场板的双槽绝缘体上硅高压器件新结构

为了提高小尺寸绝缘体上硅(SOI)器件的击穿电压,同时降低器件比导通电阻,提出了一种具有L型源极场板的双槽SOI高压器件新结构.该结构具有如下特征:首先,采用了槽栅结构,使电流纵向传导面积加宽,降低了器件的比导通电阻;其次,在漂移区引入了Si O2槽型介质层,该介质层的高电场使器件的击穿电压显著提高;第三,在槽型介质层中引入了L型源极场板,该场板调制了漂移区电场,使优化漂移区掺杂浓度大幅增加,降低了器件的比导通电阻.二维数值仿真结果表明:与传统SOI结构相比,在相同器件尺寸时,新结构的击穿电压提高了151%,比导通电阻降低了20%;在相同击穿电压时,比导通电阻降低了80%.与相同器件尺寸的双槽SOI结构相比,新结构保持了双槽SOI结构的高击穿电压特性,同时,比导通电阻降低了26%.     

具有纵向辅助耗尽衬底层的新型横向双扩散金属氧化物半导体场效应晶体管

为了优化横向双扩散金属氧化物半导体场效应晶体管(lateral double-diffused MOSFET,LDMOS)的击穿特性及器件性能,在传统LDMOS结构的基础上,提出了一种具有纵向辅助耗尽衬底层(assisted depletesubstrate layer,ADSL)的新型LDMOS.新加入的ADSL层使得漏端下方的纵向耗尽区大幅向衬底扩展,从而利用电场调制效应在ADSL层底部引入新的电场峰,使纵向电场得到优化,同时横向表面电场也因为电场调制效应而得到了优化.通过ISE仿真表明,当传统LDMOS与ADSL LDMOS的漂移区长度都是70μm时,击穿电压由462 V增大到897 V,提高了94%左右,并且优值也从0.55 MW/cm~2提升到1.24 MW/cm~2,提升了125%.因此,新结构ADSL LDMOS的器件性能较传统LDMOS有了极大的提升.进一步对ADSL层进行分区掺杂优化,在新结构的基础上,击穿电压在双分区时上升到938 V,三分区时为947 V.     

衬底浮空的新型绝缘体上硅基横向功率器件分析

针对有机半导体领域的发展要求,报道了一种能够应用于有机半导体领域衬底浮空的新型SOI LDMOS(silicon on insulator lateral double-diffused metal oxide semiconductor)功率器件,不同于传统无机半导体中SOI LDMOS功率器件,该新型器件可以与绝缘...     

Ultra-low specific on-resistance vertical double-diffused metal-oxide semiconductor with a high-k dielectric-filled extended trench

An ultra-low specific on-resistance trench gate vertical double-diffused metal-oxide semiconductor with a high-k dielectric-filled extended trench(HK TG VDMOS) is proposed in this paper.The HK TG VDMOS features a high-k(HK) trench below the trench gate.Firstly,the extended HK trench not only causes an assistant depletion of the n-drift region,but also optimizes the electric field,which therefore reduces Ron,sp and increases the breakdown voltage(BV).Secondly,the extended HK trench weakens the sensitivity of BV to the n-drift doping concentration.Thirdly,compared with the superjunction(SJ) vertical double-diffused metal-oxide semiconductor(VDMOS),the new device is simplified in fabrication by etching and filling the extended trench.The HK TG VDMOS with BV = 172 V and Ron,sp = 0.85 mΩ·cm2 is obtained by simulation;its Ron,sp is reduced by 67% and 40% and its BV is increased by about 15% and 5%,in comparison with those of the conventional trench gate VDMOS(TG VDMOS) and conventional superjunction trench gate VDMOS(SJ TG CDMOS).     

High-voltage SOI lateral MOSFET with a dual vertical field plate

A new silicon-on-insulator(SOI)power lateral MOSFET with a dual vertical field plate(VFP)in the oxide trench is proposed.The dual VFP modulates the distribution of the electric field in the drift region,which enhances the internal field of the drift region and increases the drift doping concentration of the drift region,resulting in remarkable improvements in breakdown voltage(BV)and specific on-resistance(Ron,sp).The mechanism of the VFP is analyzed and the characteristics of BV and Ron,spare discussed.It is shown that the BV of the proposed device increases from 389 V of the conventional device to 589 V,and the Ron,sp decreases from 366 m·cm2to 110 m·cm2.     

A low on-resistance triple RESURF SOI LDMOS with planar and trench gate integration

A low on-resistance(Ron,sp) integrable silicon-on-insulator(SOI) n-channel lateral double-diffused metal-oxide-semiconductor(LDMOS) is proposed and its mechanism is investigated by simulation.The LDMOS has two features:the integration of a planar gate and an extended trench gate(double gates(DGs));and a buried P-layer in the N-drift region,which forms a triple reduced surface field(RESURF)(TR) structure.The triple RESURF not only modulates the electric field distribution,but also increases N-drift doping,resulting in a reduced specific on-resistance(Ron,sp) and an improved breakdown voltage(BV) in the off-state.The DGs form dual conduction channels and,moreover,the extended trench gate widens the vertical conduction area,both of which further reduce the Ron,sp.The BV and Ron,sp are 328 V and 8.8 m.cm2,respectively,for a DG TR metal-oxide-semiconductor field-effect transistor(MOSFET) by simulation.Compared with a conventional SOI LDMOS,a DG TR MOSFET with the same dimensional device parameters as those of the DG TR MOSFET reduces Ron,sp by 59% and increases BV by 6%.The extended trench gate synchronously acts as an isolation trench between the high-voltage device and low-voltage circuitry in a high-voltage integrated circuit,thereby saving the chip area and simplifying the fabrication processes.     

A low specific on-resistance SOI LDMOS with a novel junction field plate

A low specific on-resistance SO1 LDMOS with a novel junction field plate （JFP） is proposed and investigated theo- retically. The most significant feature of the JFP LDMOS is a PP-N junction field plate instead of a metal field plate. The unique structure not only yields charge compensation between the JFP and the drift region, but also modulates the surface electric field. In addition, a trench gate extends to the buffed oxide layer （BOX） and thus widens the vertical conduction area. As a result, the breakdown voltage （BV） is improved and the specific on-resistance （Ron,sp） is decreased significantly. It is demonstrated that the BV of 306 V and the Ron,sp of 7.43 mΩ.cm2 are obtained for the JFP LDMOS. Compared with those of the conventional LDMOS with the same dimensional parameters, the BV is improved by 34.8%, and the Ron,sp is decreased by 56.6% simultaneously. The proposed JFP LDMOS exhibits significant superiority in terms of the trade-off between BV and Ron,sp. The novel JFP technique offers an alternative technique to achieve high blocking voltage and large current capacity for power devices.     

A low specific on-resistance SOI MOSFET with dual gates and a recessed drain

A low specific on-resistance(Ron,sp) integrable silicon-on-insulator(SOI) metal-oxide semiconductor field-effect transistor(MOSFET) is proposed and investigated by simulation.The MOSFET features a recessed drain as well as dual gates,which consist of a planar gate and a trench gate extended to the buried oxide layer(BOX)(DGRD MOSFET).First,the dual gates form dual conduction channels,and the extended trench gate also acts as a field plate to improve the electric field distribution.Second,the combination of the trench gate and the recessed drain widens the vertical conduction area and shortens the current path.Third,the P-type top layer not only enhances the drift doping concentration but also modulates the surface electric field distributions.All of these sharply reduce Ron,sp and maintain a high breakdown voltage(BV).The BV of 233 V and Ron,sp of 4.151 mΩ·cm2(VGS = 15 V) are obtained for the DGRD MOSFET with 15-μm half-cell pitch.Compared with the trench gate SOI MOSFET and the conventional MOSFET,Ron,sp of the DGRD MOSFET decreases by 36% and 33% with the same BV,respectively.The trench gate extended to the BOX synchronously acts as a dielectric isolation trench,simplifying the fabrication processes.     

A low specific on-resistance SOI MOSFET with dual gates and recessed drain

A low specific on-resistance (R_on,sp) integrable silicon-on-insulator (SOI) metal-oxide semiconductor field-effect transistor (MOSFET) is proposed and investigated by simulation. The MOSFET features a recessed drain as well as dual gates which consist of a planar gate and a trench gate extended to the buried oxide layer (BOX) (DGRD MOSFET). First, the dual gates form dual conduction channels, and the extended trench gate also acts as a field plate to improve the electric field distribution. Second, the combination of the trench gate and the recessed drain widens the vertical conduction area and shortens the current path. Third, the P-type top layer not only enhances the drift doping concentration but also modulates the surface electric field distributions. All of these sharply reduce R_on,sp and maintain a high breakdown voltage (BV). The BV of 233 V and R_on,sp of 4.151 mΩ·cm² (V_GS=15 V) are obtained for the DGRD MOSFET with 15-μm half-cell pitch. Compared with the trench gate SOI MOSFET and the conventional MOSFET, R_on,sp of the DGRD MOSFET decreases by 36% and 33% with the same BV, respectively. The trench gate extended to the BOX synchronously acts as a dielectric isolation trench, simplifying the fabrication processes.     

Ultra-low specific on-resistance high-voltage vertical double diffusion metal–oxide–semiconductor field-effect transistor with continuous electron accumulation layer

A new ultra-low specific on-resistance(Ron,sp) vertical double diffusion metal–oxide–semiconductor field-effect transistor(VDMOS) with continuous electron accumulation(CEA) layer, denoted as CEA-VDMOS, is proposed and its new current transport mechanism is investigated. It features a trench gate directly extended to the drain, which includes two PN junctions. In on-state, the electron accumulation layers are formed along the sides of the extended gate and introduce two continuous low-resistance current paths from the source to the drain in a cell pitch. This mechanism not only dramatically reduces the Ron,sp but also makes the Ron,sp almost independent of the n-pillar doping concentration(Nn). In off-state, the depletion between the n-pillar and p-pillar within the extended trench gate increases the Nn, and further reduces the Ron,sp.Especially, the two PN junctions within the trench gate support a high gate–drain voltage in the off-state and on-state, respectively. However, the extended gate increases the gate capacitance and thus weakens the dynamic performance to some extent. Therefore, the CEA-VDMOS is more suitable for low and medium frequencies application. Simulation indicates that the CEA-VDMOS reduces the Ron,sp by 80% compared with the conventional super-junction VDMOS(CSJ-VDMOS)at the same high breakdown voltage(BV).     

Low on-resistance high-voltage lateral double-diffused metal oxide semiconductor with a buried improved super-junction layer

A novel low specific on-resistance （Ron,sp） lateral double-diffused metal oxide semiconductor （LDMOS） with a buried improved super-junction （BISJ） layer is proposed. A super-junction layer is buried in the drift region and the P pillar is split into two parts with different doping concentrations. Firstly, the buried super-junction layer causes the multiple-direction assisted depletion effect. The drift region doping concentration of the BISJ LDMOS is therefore much higher than that of the conventional LDMOS. Secondly, the buried super-junction layer provides a bulk low on-resistance path. Both of them reduce Ron,sp greatly. Thirdly, the electric field modulation effect of the new electric field peak introduced by the step doped P pillar improves the breakdown voltage （BV）. The BISJ LDMOS exhibits a BV of 300 V and Ron,sp of 8.08 mΩ·cm2 which increases BV by 35% and reduces Ron,sp by 60% compared with those of a conventional LDMOS with a drift length of 15 μm, respectively.     

Ultra-low on-resistance high voltage (>600 V) SOI MOSFET with a reduced cell pitch

A low specific on-resistance (R S,on) silicon-on-insulator (SOI) trench MOSFET (metal-oxide-semiconductor-field-effect-transistor) with a reduced cell pitch is proposed.The lateral MOSFET features multiple trenches:two oxide trenches in the drift region and a trench gate extended to the buried oxide (BOX) (SOI MT MOSFET).Firstly,the oxide trenches increase the average electric field strength along the x direction due to lower permittivity of oxide compared with that of Si;secondly,the oxide trenches cause multiple-directional depletion,which improves the electric field distribution and enhances the reduced surface field (RESURF) effect in the SOI layer.Both of them result in a high breakdown voltage (BV).Thirdly,the oxide trenches cause the drift region to be folded in the vertical direction,leading to a shortened cell pitch and a reduced R S,on.Fourthly,the trench gate extended to the BOX further reduces R S,on,owing to the electron accumulation layer.The BV of the MT MOSFET increases from 309 V for a conventional SOI lateral double diffused metal-oxide semiconductor (LDMOS) to 632 V at the same half cell pitch of 21.5 μm,and R S,on decreases from 419 m · cm 2 to 36.6 m · cm 2.The proposed structure can also help to dramatically reduce the cell pitch at the same breakdown voltage.