Hybrid silicon evanescent approach to optical interconnects |
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Authors: | Di Liang Alexander W Fang Hui-Wen Chen Matthew N Sysak Brian R Koch Erica Lively Omri Raday Ying-Hao Kuo Richard Jones and John E Bowers |
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Institution: | (1) Department of Electrical and Computer Engineering, University of California, Santa Barbara, CA 91206, USA;(2) Intel Corporation, 2200 Mission College Blvd, SC12-326, Santa Clara, CA 95054, USA;(3) Intel Corporation, S.B.I. Park Har Hotzvim, Jerusalem, 91031, Israel |
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Abstract: | We discuss the recently developed hybrid silicon evanescent platform (HSEP), and its application as a promising candidate
for optical interconnects in silicon. A number of key discrete components and a wafer-scale integration process are reviewed.
The motivation behind this work is to realize silicon-based photonic integrated circuits possessing unique advantages of III–V
materials and silicon-on-insulator waveguides simultaneously through a complementary metal-oxide semiconductor fabrication
process. Electrically pumped hybrid silicon distributed feedback and distributed Bragg reflector lasers with integrated hybrid
silicon photodetectors are demonstrated coupled to SOI waveguides, serving as the reliable on-chip single-frequency light
sources. For the external signal processing, Mach–Zehnder interferometer modulators are demonstrated, showing a resistance-capacitance-limited,
3 dB electrical bandwidth up to 8 GHz and a modulation efficiency of 1.5 V mm. The successful implementation of quantum well
intermixing technique opens up the possibility to realize multiple III–V bandgaps in this platform. Sampled grating DBR devices
integrated with electroabsorption modulators (EAM) are fabricated, where the bandgaps in gain, mirror, and EAM regions are
1520, 1440 and 1480 nm, respectively. The high-temperature operation characteristics of the HSEP are studied experimentally
and theoretically. An overall characteristic temperature (T
0) of 51°C, an above threshold characteristic temperature (T
1) of 100°C, and a thermal impedance (Z
T
) of 41.8°C/W, which agrees with the theoretical prediction of 43.5°C/W, are extracted from the Fabry–Perot devices. Scaling
this platform to larger dimensions is demonstrated up to 150 mm wafer diameter. A vertical outgassing channel design is developed
to accomplish high-quality III–V epitaxial transfer to silicon in a timely and dimension-independent fashion. |
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Keywords: | PACS" target="_blank">PACS 71 20 Mq 71 55 Eq 42 79 Ta 42 55 Px |
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