基于FPGA的DDR3控制器存储设计与验证

DDR3 SDRAM是第三代双倍数据传输速率同步动态随机存储器，DDR3具有高速率、低电压、低功耗等特点1]2]。在DDR3控制器的实际使用中，如何将用户需要存储的数据在DDR3中快速存储非常重要，如果数据被送到DDR3接口的速度低，则会影响DDR3的存储速度，同时影响DDR3的实际应用，因此，针对DDR3存储器设计存储控制有重要的意义2]。基于此设计主要分为低速读写控制与高速流读写控制，低速读写控制主要用于小数据量的操作，高速流读写控制主要用于批量数据的存储操作。此设计在FPGA上通过了大量数据读写的验证，证明数据存储的正确性。经过测试，在高速流读写模式下，DDR3存储控制设计的带宽利用率最大为66.4%。此设计在功能和性能上均符合系统总体设计的要求。

Design and Verification of DDR3 Controller Based on FPGA

DDR3 SDRAM is the third generation of double data rate synchronous dynamic random access memory, which has characteristics high speed, low voltage, low power consumption and others1]2]. In the actual use of DDR3 controller, it is important about how will the user needs for data storage in DDR3 quickly. If the speed of sending data to the DDR3 interface is low, it will affect the storage speed of DDR3. Therefore, the design of DDR3 memory storage control has important significance. This design is mainly includes low speed to read-write control which is used mainly for small amount of data read and write operation, and high speed flow read-write control which is mainly used for the storage of mass data operation. This design is tested based on FPGA by a large amount of data reading and writing, it proves the correctness of data storage. In the high speed stream to read or write mode, the DDR3 control design to maximize the utilization ratio of bandwidth is 66.4%, The function and performance of the design can satisfy the system requirements of the overall design.