1200 V碳化硅功率MOSFET低温特性的实验表征及分析

碳化硅功率MOSFET是宽禁带功率半导体器件的典型代表,具有优异的电气性能。基于低温环境下的应用需求,研究了1200 V碳化硅功率MOSFET在77.7 K至300 K温区的静/动态特性,定性分析了温度对碳化硅功率MOSFET性能的影响。实验结果显示,温度从300 K降低至77.7 K时,阈值电压上升177.24%,漏-源极击穿电压降低32.99%,栅极泄漏电流降低82.51%,导通电阻升高1142.28%,零栅压漏电流降低89.84%(300 K至125 K)。双脉冲测试显示,开通时间增大8.59%,关断时间降低16.86%,开关损耗增加48%。分析发现,碳化硅功率MOSFET较高的界面态密度和较差的沟道迁移率,是导致其在低温下性能劣化的主要原因。     

Effect of gate engineering in JLSRG MOSFET to suppress SCEs: An analytical study

In this work, an analytical model of gate-engineered junctionless surrounding gate MOSFET (JLSRG) has been proposed to uncover its potential benefit to suppress short-channel effects (SCEs). Analytical modelling of centre potential for gate-engineered JLSRG devices has been developed using parabolic approximation method. From the developed centre potential, the parameters like threshold voltage, surface potential, Electric Field, Drain-induced Barrier Lowering (DIBL) and subthershold swing are determined. A nice agreement between the results obtained from the model and TCAD simulation demonstrates the validity and correctness of the model. A comparative study of the efficacy to suppress SCEs for Dual-Material (DM) and Single-Material (SM) junctionless surrounding gate MOSFET of the same dimensions has also been carried out. Result indicates that TM-JLSRG devices offer a noticeable enhancement in the efficacy to suppress SCEs by as compared to SM-JLSRG and DM-JLSRG device structures. The effect of different length ratios of three channel regions related to three different gate materials of TM-JLSRG structure on the SCEs have also been discussed. As a result, we demonstrate that TM-JLSRG device can be considered as a competitive contender to the deep-submicron mainstream MOSFETs for low-power VLSI applications.     

高功率窄脉宽半导体激光激励器设计

为了获得高功率窄脉宽半导体激光,设计了半导体激光器相应的激励单元,论述MOSFET作为高速开关的工作机理,分析基于MOSFET作为高速开关产生窄的大电流脉冲的电路模型.为了使MOSFET开关速度尽可能快,根据前述分析,提出推挽式MOSFET栅极驱动方式并设计了触发窄脉冲的发生电路.当激光二极管接入放电回路时,实验表明:激光二极管输出光的峰值功率可达67.5 W,脉宽约为20 ns.最后,简要分析了影响光脉冲宽度的因素.     

纳米尺度MOSFET过剩噪声的定性分析

最近实验表明纳米尺度MOSFET中的过剩噪声主要为散粒噪声,而此前研究认为MOSFET中不存在散粒噪声,短沟道MOSFET中的过剩噪声为热噪声. 本文基于器件电流模型分析散粒噪声取代热噪声成为过剩噪声主要成分的转变条件,根据该条件对纳米尺度MOSFET噪声特性的预测与文献报道的实验现象、模拟结果以及介观散粒噪声相关结论相符合. 关键词： 散粒噪声 过剩噪声 纳米尺度MOSFET     

Investigation of laterally single-diffused metal oxide semiconductor (LSMOS) field effect transistor

We propose a distinct approach to implement a laterally single diffused metal-oxide-semiconductor (LSMOS) FET with only one impurity doped p-n junction. In the LSMOS, a single p-n junction is first created using lateral dopant diffusion. The channel is formed in the p region of the p-n junction and the n region acts as the drift region. Two distinct metals of different work function are used to form the “n⁺” source/drain regions and “p⁺” body contact using the charge plasma concept. We demonstrate that the LSMOS is similar in performance to a laterally double diffused metal-oxide-semiconductor (LDMOS) although it has only one impurity doped p-n junction. The LSMOS exhibits a breakdown voltage of ∼50.0 V, an average ON-resistance of 48.7 mΩ-mm² and a peak transconductance of 53.6 μS/μm similar to that of a comparable LDMOS.     

Extraordinarily high drive currents in asymmetrical double-gate MOSFETs

Numerical simulation results derived from a Schrödinger–Poisson tool applied to scaled double-gate (DG) MOSFETs, supplemented by analytical characterizations of the pertinent physics, are presented to give insight concerning the near-ideal features of DG devices and to explain how the low-voltage drive current of the asymmetrical DG MOSFET, having only one predominant channel, can be comparable to, and even higher than, that of the symmetrical-gate counterpart designed to have the same off-state current.     

Interface control of high-k gate dielectrics on Ge

Important progress has been made in the passivation of Ge/gate dielectric interfaces. One important approach is by thermally oxidized GeO₂ interface and ALD high-k layers, with an interface state density D_it ∼ 2 × 10¹¹ cm⁻² eV⁻¹. Another approach is with an epi-Si/SiO₂ interface, resulting in similar D_it. Hysteresis and V_th shift, however, are still not optimal. Extensive material characterization and theoretical insights help us understanding the root cause of these remaining issues and show the way to improved interface control.     

TRUS-probe integrated MOSkin detectors for rectal wall in vivo dosimetry in HDR brachytherapy: In phantom feasibility study

The increasing complexity and high amount of dose per fraction delivered in prostate high dose rate (HDR) brachytherapy treatments call for the implementation of accurate and effective methods for the systematic and independent quality control of the overall treatment procedure. In this study, MOSkin detectors were placed on a trans-rectal ultrasound (TRUS) probe with the aim of performing both imaging and real time rectal wall in vivo dosimetry with the use of just one single instrument. After an adequate calibration of the detectors, which was carried out in a solid water phantom, the use of MOSkins integrated to the TRUS probe was studied in a gel phantom with a typical (simplified) prostate implant. Measured and calculated doses from the treatment planning system were compared, with a resulting very low average discrepancy of −0.6 ± 2.6%. The results are very promising and of particular clinical importance, however, further in vivo investigation is planned to validate the proposed method.     

A two-dimensional analytical subthreshold behavior model for junctionless dual-material cylindrical surrounding-gate MOSFETs

A two-dimensional analytical subthreshold behavior model for junctionless dual-material cylindrical surrounding- gate （JLDMCSG） metal-oxide-semiconductor field-effect transistors （MOSFETs） is proposed. It is derived by solving the two-dimensional Poisson＇s equation in two continuous cylindrical regions with any simplifying assumption. Using this analytical model, the subthreshold characteristics of JLDMCSG MOSFETs are investigated in terms of channel electro- static potential, horizontal electric field, and subthreshold current. Compared to junctionless single-material cylindrical surrounding-gate MOSFETs, JLDMCSG MOSFETs can effectively suppress short-channel effects and simultaneously im- prove carrier transport efficiency. It is found that the subthreshold current of JLDMCSG MOSFETs can be significantly reduced by adopting both a thin oxide and thin silicon channel. The accuracy of the analytical model is verified by its good agreement with the three-dimensional numerical simulator ISE TCAD.     

A two-dimensional analytical model for channel potential and threshold voltage of short channel dual material gate lightly doped drain MOSFET

An analytical model for the channel potential and the threshold voltage of the short channel dual-material-gate lightly doped drain （DMG-LDD） metal-oxide-semiconductor field-effect transistor （MOSFET） is presented using the parabolic approximation method. The proposed model takes into account the effects of the LDD region length, the LDD region doping, the lengths of the gate materials and their respective work functions, along with all the major geometrical parameters of the MOSFET. The impact of the LDD region length, the LDD region doping, and the channel length on the channel potential is studied in detail. Furthermore, the threshold voltage of the device is calculated using the minimum middle channel potential, and the result obtained is compared with the DMG MOSFET threshold voltage to show the improvement in the threshold voltage roll-off. It is shown that the DMG-LDD MOSFET structure alleviates the problem of short channel effects （SCEs） and the drain induced barrier lowering （DIBL） more efficiently. The proposed model is verified by comparing the theoretical results with the simulated data obtained by using the commercially available ATLASTM 2D device simulator.